DAC12DL3200
- 12-bit resolution
- Maximum input and output sample rate:
- Single channel up to 6.4 GSPS
- Dual channel up to 3.2 GSPS
- Multi-Nyquist operating modes:
- Single channel modes: NRZ, RTZ, RF
- Dual channel modes: NRZ, RTZ, RF, 2xRF
- Low latency through device: 6 to 8 ns
- Matching transmit capabilities to the low latency receiver ADC12DL3200
- DAC and ADC combined latency < 15 ns (not including FPGA)
- Parallel DDR LVDS interface:
- Source synchronous interface to simplify timing:
- 24 or 48 LVDS pairs up to 1.6 Gbps
- 1 LVDS DDR clock per 12-bit bus
- Output frequency range: > 8 GHz
- Full-scale current: 21 mA
- Simplified clocking and synchronization
- SYSREF windowing eases setup and hold times
- On-chip direct digital synthesizer (DDS)
- Single-tone and two-tone sine wave generation
- 32 x 32-bit numerically controlled oscillators
- Fast frequency hopping capability (< 500 ns)
- Synchronous CMOS frequency/phase input
- Performance at fOUT = 4.703 GHz, 6.4 GSPS, RF mode
- Output power: –3 dBm
- Noise floor (70 MHz offset): –147 dBc/Hz
- SFDR: 60 dBc
- Power supplies: 1.0 V, 1.8 V, –1.8 V
- Power consumption: 1.49 W (2-ch, RF mode, 3.2 GSPS)
- Package: 256-Ball FCBGA (17x17 mm, 1 mm pitch)
The DAC12DL3200 is a very low latency, dual channel, RF sampling digital-to-analog converter (DAC) capable of input and output rates of up to 3.2-GSPS in dual channel mode or 6.4-GSPS in single channel mode. The DAC can transmit signal bandwidths beyond 2 GHz at carrier frequencies approaching 8 GHz when using the multi-Nyquist output modes. The high output frequency range enables direct sampling through C-band (8 GHz) and beyond.
The DAC12DL3200 can be used as an I/Q baseband DAC in dual channel mode. The high sampling rate and output frequency range also makes the DAC12DL3200 capable of arbitrary waveform generation (AWG) and direct digital synthesis (DDS). An integrated DDS block enables single tone and two tone generation on chip.
The DAC12DL3200 has a parallel LVDS interface that consists of up to 48 LVDS pairs and 4 DDR LVDS clocks. A strobe signal is used to synchronize the interface which can be sent over the least significant bit (LSB) or optionally over dedicated strobe LVDS lanes. Each LVDS pair is capable of up to 1.6 Gbps. Multi-device synchronization is supported using a synchronization signal (SYSREF) and is compatible with JESD204B/C clocking devices. SYSREF windowing eases synchronization in multi-device systems.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DAC12DL3200 up to 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel 12-bit Digital-to-Analog Converter (DAC) with Low-Latency LVDS Interface datasheet (Rev. B) | PDF | HTML | 2022年 6月 27日 |
| User guide | DAC12DL3200 Evaluation Module User's Guide (Rev. A) | PDF | HTML | 2022年 5月 23日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
DAC12DL3200EVM — 適用於 12 位元、雙路 3.2 GSPS 或單路 6.4-GSPS、射頻取樣 DAC 的 DAC12DL3200 評估模組
DAC12DL3200 評估模組 (EVM) 是用於評估 DAC12DL3200 的平台，是一款超低延遲、雙通道、12 位元、射頻取樣數位轉類比轉換器 (DAC)，在雙通道模式下能以高達 3.2 GSPS 或單通道模式下 6.4 GSPS 的取樣率運作。
DAC12DL3200 在使用多個 Nyquist 輸出模式時，在載波頻率接近 8 GHz 時，可以傳輸超過 2 GHz 的訊號帶寬。DAC12DL3200EVM 裝置輸入資料會透過高速低電壓差動訊號 (LVDS) 介面傳送。
EVM 隨附之 LMX2592 時脈合成器和 LMK04828 JESD204B (...)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCBGA (ACF) | 256 | Ultra Librarian |
| FCBGA (ALJ) | 256 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。