LMK00725
- Five 3.3V Differential LVPECL Outputs
- Additive Jitter: 43 fs RMS (typ) @ 312.5 MHz
- Noise Floor (≥1 MHz offset):
–158 dBc/Hz (typ) @ 312.5 MHz - Output Frequency: 650 MHz (max)
- Output Skew: 35 ps (max)
- Part-to-Part Skew: 100 ps (max)
- Propagation Delay: 0.37 ns (max)
- Two Differential Input Pairs (pin-selectable)
- CLKx, nCLK Input Pairs can accept LVPECL,
LVDS, HCSL, SSTL, LVHSTL, or Single-Ended
Signals
- CLKx, nCLK Input Pairs can accept LVPECL,
- Synchronous Clock Enable
- Power Supply: 3.3V ±5%
- Package: 20-Lead TSSOP
- Industrial Temperature Range: –40°C to +85°C
The LMK00725 is a low skew, high-performance clock fanout buffer which can distribute up to five 3.3V LVPECL outputs from one of two inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable pin is asserted or de-asserted. The low additive jitter and phase noise floor and ensured output and part-to-part skew characteristics make the LMK00725 ideal for applications demanding high performance and repeatability.
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檢視所有 2 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | LMK00725 Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buf datasheet (Rev. A) | 2013年 10月 30日 | |
| EVM User's guide | LMK00725EVM User’s Guide | 2013年 9月 6日 |
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CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 20 | Ultra Librarian |
訂購與品質
內含資訊：
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- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
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