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SN74CBTLV16292

現行

具有內部下拉電阻器的 3.3-V、1:1 (SPST)、12 通道通用型 FET 匯流排開關

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產品規格表

SN74CBTLV16292

現行
產品規格表 立即訂購

產品詳細資料

Configuration 2:1 SPDT Number of channels 12 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog Ron (typ) (Ω) 3 CON (typ) (pF) 22.5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 85 Features Break-before-make, Powered-off protection Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
Configuration 2:1 SPDT Number of channels 12 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog Ron (typ) (Ω) 3 CON (typ) (pF) 22.5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 85 Features Break-before-make, Powered-off protection Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
SSOP (DL) 56 190.647 mm² 18.42 x 10.35 TSSOP (DGG) 56 113.4 mm² 14 x 8.1 TVSOP (DGV) 56 72.32 mm² 11.3 x 6.4
  • Member of the Texas Instruments Widebus™ Family
  • 4- Switch Connection Between Two Ports
  • Rail-to-Rail Switching on Data I/O Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Make-Before-Break Feature
  • Internal 500- Pulldown Resistors to Ground
  • Latch-Up Performance Exceeds 250 mA Per JESD 17

Widebus is a trademark of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • 4- Switch Connection Between Two Ports
  • Rail-to-Rail Switching on Data I/O Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Make-Before-Break Feature
  • Internal 500- Pulldown Resistors to Ground
  • Latch-Up Performance Exceeds 250 mA Per JESD 17

Widebus is a trademark of Texas Instruments.

The SN74CBTLV16292 is a 12-bit 1-of-2 high-speed FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

When the select (S) input is low, port A is connected to port B1, and RINT is connected to port B2. When S is high, port A is connected to port B2, and RINT is connected to port B1.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

The SN74CBTLV16292 is a 12-bit 1-of-2 high-speed FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

When the select (S) input is low, port A is connected to port B1, and RINT is connected to port B2. When S is high, port A is connected to port B2, and RINT is connected to port B1.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.
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類型 標題 日期
* Data sheet SN74CBTLV16292 datasheet (Rev. K) 2003年 10月 13日
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022年 6月 2日
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021年 12月 1日
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 2021年 1月 6日
Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note How to Select Little Logic (Rev. A) 2016年 7月 26日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
More literature Digital Bus Switch Selection Guide (Rev. A) 2004年 11月 10日
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note Bus FET Switch Solutions for Live Insertion Applications 2003年 2月 7日
Application note Texas Instruments Little Logic Application Report 2002年 11月 1日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
User guide CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) 1998年 12月 1日

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模擬型號

HSpice Model of SN74CBTLV16292

SCDJ013.ZIP (41 KB) - HSpice Model
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模擬型號

SN74CBTLV16292 IBIS Model

SCDM064.ZIP (29 KB) - IBIS Model
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SSOP (DL) 56 Ultra Librarian
TSSOP (DGG) 56 Ultra Librarian
TVSOP (DGV) 56 Ultra Librarian
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