SN74LV138AT

Name: SN74LV138AT
Brand: TI
SKU: SN74LV138AT
Price: 0.103 USD

現行

3 線路到 8 線路解碼器/解多工器

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產品規格表

document-pdfAcrobat SN74LV138AT datasheet (英文)

SN74LV138AT

現行

產品規格表

立即訂購

產品詳細資料

Technology family

LV-AT

Number of channels

1

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Supply current (max) (µA)

20

Technology family

LV-AT

Number of channels

1

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Supply current (max) (µA)

20

SOIC (D)

16

59.4 mm² 9.9 x 6

SSOP (DB)

16

48.36 mm² 6.2 x 7.8

TSSOP (PW)

16

32 mm² 5 x 6.4

TVSOP (DGV)

16

23.04 mm² 3.6 x 6.4

VQFN (RGY)

16

14 mm² 4 x 3.5

Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V V_CC Operation
Max t_pd of 7.6 ns at 5 V
Typical V_OLP (Output Ground Bounce)<0.8 V at V_CC = 5 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)>>2.3 V at V_CC = 5 V, T_A = 25°C
Support Mixed-Mode Voltage Operation on All Ports
I_off Supports Partial-Power Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V V_CC Operation
Max t_pd of 7.6 ns at 5 V
Typical V_OLP (Output Ground Bounce)<0.8 V at V_CC = 5 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)>>2.3 V at V_CC = 5 V, T_A = 25°C
Support Mixed-Mode Voltage Operation on All Ports
I_off Supports Partial-Power Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

The SN74LV138AT is a 3-line to 8-line decoder/demultiplexer, designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2A, G2B) select one of eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

This device is fully specified for partial-power-down application susing I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LV138AT is a 3-line to 8-line decoder/demultiplexer, designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2A, G2B) select one of eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

This device is fully specified for partial-power-down application susing I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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