SN74LVC138A-Q1

Name: SN74LVC138A-Q1
Brand: TI
SKU: SN74LVC138A-Q1
Price: 0.231 USD

現行

汽車類 3 線路至 8 線路解碼器/解多工器

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產品規格表

document-pdfAcrobat 3-Line to 8-Line Decoder/Demultiplexer datasheet (Rev. B) (英文)

SN74LVC138A-Q1

現行

產品規格表

立即訂購

產品詳細資料

Technology family

LVC

Number of channels

1

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Supply current (max) (µA)

10

Technology family

LVC

Number of channels

1

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Supply current (max) (µA)

10

SOIC (D)

16

59.4 mm² 9.9 x 6

TSSOP (PW)

16

32 mm² 5 x 6.4

Qualified for Automotive Applications
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Operates From 2 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 5.8 ns at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C

Qualified for Automotive Applications
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Operates From 2 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 5.8 ns at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C

The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation.

The device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation.

The device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

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車用 3 線路至 8 線路反相解碼器/解多工器 Different voltage range (2V to 6V), longer average propagation delay (7ns)

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	類型	標題	日期
*	Data sheet	3-Line to 8-Line Decoder/Demultiplexer datasheet (Rev. B)	2008年 2月 12日
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	2021年 7月 26日
	Selection guide	Little Logic Guide 2018 (Rev. G)	2018年 7月 6日
	Selection guide	Logic Guide (Rev. AB)	2017年 6月 12日
	Application note	How to Select Little Logic (Rev. A)	2016年 7月 26日
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	2015年 12月 2日
	More literature	Automotive Logic Devices Brochure	2014年 8月 27日
	User guide	LOGIC Pocket Data Book (Rev. B)	2007年 1月 16日
	Product overview	Design Summary for WCSP Little Logic (Rev. B)	2004年 11月 4日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	2004年 7月 8日
	Application note	Selecting the Right Level Translation Solution (Rev. A)	2004年 6月 22日
	User guide	Signal Switch Data Book (Rev. A)	2003年 11月 14日
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits	2003年 11月 6日
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)	2002年 12月 18日
	Application note	Texas Instruments Little Logic Application Report	2002年 11月 1日
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	2002年 8月 29日
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	2002年 6月 13日
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	2002年 5月 22日
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	2002年 5月 10日
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS	2002年 3月 27日
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	1997年 12月 1日
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	1997年 8月 1日
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	1997年 6月 1日
	Application note	LVC Characterization Information	1996年 12月 1日
	Application note	Input and Output Characteristics of Digital Integrated Circuits	1996年 10月 1日
	Application note	Live Insertion	1996年 10月 1日
	Design guide	Low-Voltage Logic (LVC) Designer's Guide	1996年 9月 1日
	Application note	Understanding Advanced Bus-Interface Products Design Guide	1996年 5月 1日

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SOIC (D)	16	Ultra Librarian
TSSOP (PW)	16	Ultra Librarian

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SN74LVC138A-Q1

汽車類 3 線路至 8 線路解碼器/解多工器

SN74LVC138A-Q1

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