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TDA4VP-Q1

現行

用於具有 Arm® Cortex®-A72、圖形、AI 和視訊協同處理器的 L2、L3 領域控制器的車用 SoC

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TDA4VP-Q1

現行
產品規格表 立即訂購

產品詳細資料

Arm CPU 8 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors MCU Island of 2 Arm Cortex-R5F (lockstep opt), SoC main of 6 Arm Corex-R5F (lockstep opt) CPU 64-bit Graphics acceleration 1 3D Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 4-Port 1Gb switch PCIe 2 PCIe Gen 3 Hardware accelerators 1 depth and motion accelerator, 1 video encode/decode accelerator, 2 vision pre-processing accelerators, 3 deep learning accelerators Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Trusted execution environment Rating Automotive Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 125
Arm CPU 8 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors MCU Island of 2 Arm Cortex-R5F (lockstep opt), SoC main of 6 Arm Corex-R5F (lockstep opt) CPU 64-bit Graphics acceleration 1 3D Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 4-Port 1Gb switch PCIe 2 PCIe Gen 3 Hardware accelerators 1 depth and motion accelerator, 1 video encode/decode accelerator, 2 vision pre-processing accelerators, 3 deep learning accelerators Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Trusted execution environment Rating Automotive Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 125
FCBGA (ALY) 1414 961 mm² 31 x 31

Processor cores:

  • Up to Four C7x floating point, vector DSP, up to 1.0 GHz, 320 GFLOPS, 1024 GOPS
  • Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32 TOPS (8b) at 1.0 GHz
  • Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Eight Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz
    • 2MB shared L2 cache per quad-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Eight Arm Cortex-R5F MCUs at up to 1.0 GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Six Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to 4x32-b bus with inline ECC up to 68 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 3x512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Safety-related certification
      • ISO 26262 planned
  • AEC-Q100 qualilfied on part number variants ending in Q1

    Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated ethernet switch supporting up to 8 (TDA4xH) or 4 (TDA4xP) external ports
    • Two ports support 5Gb, 10Gb USXGMII/XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 (TDA4xH) or 1 (TDA4xP) QSGMII can be enabled and uses all 8 or 4 internal lanes
  • Up to 4x2-L/2x4L (TDA4xH) or 2x2L/1x4L (TDA4xP) PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Three CSI2.0 4L RX plus Two CSI2.0 4L TX

    Ethernet:

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Display subsystem:

  • Two DSI 4L TX (up to 2.5k)
  • One eDP/DP interface with Multi-Display Support (MST)
  • One DPI

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • H.264/H.265 Encode/Decode, up to 960MP/s (TDA4xH) or 480MP/s (TDA4xP)

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

Processor cores:

  • Up to Four C7x floating point, vector DSP, up to 1.0 GHz, 320 GFLOPS, 1024 GOPS
  • Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32 TOPS (8b) at 1.0 GHz
  • Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Eight Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz
    • 2MB shared L2 cache per quad-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Eight Arm Cortex-R5F MCUs at up to 1.0 GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Six Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to 4x32-b bus with inline ECC up to 68 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 3x512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Safety-related certification
      • ISO 26262 planned
  • AEC-Q100 qualilfied on part number variants ending in Q1

    Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated ethernet switch supporting up to 8 (TDA4xH) or 4 (TDA4xP) external ports
    • Two ports support 5Gb, 10Gb USXGMII/XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 (TDA4xH) or 1 (TDA4xP) QSGMII can be enabled and uses all 8 or 4 internal lanes
  • Up to 4x2-L/2x4L (TDA4xH) or 2x2L/1x4L (TDA4xP) PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Three CSI2.0 4L RX plus Two CSI2.0 4L TX

    Ethernet:

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Display subsystem:

  • Two DSI 4L TX (up to 2.5k)
  • One eDP/DP interface with Multi-Display Support (MST)
  • One DPI

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • H.264/H.265 Encode/Decode, up to 960MP/s (TDA4xH) or 480MP/s (TDA4xP)

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 devices a great fit for several imaging, vision, radar, sensor fusion and AI applications such as: Robotics, Mobile machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways, Retail automation, Medical Imaging, and so on. The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. A single instance of the new “MMAv2” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate eight core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Eight Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated IMG BXS-4-64 GPU offers up to 50 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 family also includes an MCU island eliminating the need for an external system microcontroller.

The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 devices a great fit for several imaging, vision, radar, sensor fusion and AI applications such as: Robotics, Mobile machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways, Retail automation, Medical Imaging, and so on. The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. A single instance of the new “MMAv2” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate eight core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Eight Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated IMG BXS-4-64 GPU offers up to 50 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 family also includes an MCU island eliminating the need for an external system microcontroller.
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類型 標題 日期
* Data sheet TDA4VH-Q1, TDA4AH-Q1, TDA4VP-Q1, TDA4AP-Q1 Jacinto™ Processors datasheet (Rev. B) PDF | HTML 2023年 12月 15日
* Errata J784S4, TDA4AP, TDA4VP, TDA4AH, TDA4VH, AM69A Processors Silicon Revision 1.0 (Rev. B) PDF | HTML 2024年 7月 24日
User guide J784S4, TDA4VH, TDA4AH, TDA4VP, TDA4AP, AM69 Power Estimation Tool User’s Guide (Rev. A) 2024年 12月 23日
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 2024年 8月 5日
User guide J784S4 J742S2 Technical Reference Manual (Rev. D) 2024年 7月 24日
Application note Debugging GPU Driver Issues on TDA4x and AM6x Devices PDF | HTML 2024年 6月 20日
Application note Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 2024年 6月 4日
Application note MMC SW Tuning Algorithm (Rev. A) PDF | HTML 2024年 5月 14日
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 2024年 4月 4日
User guide SK-AM69 Processor Start Kit User's Guide (Rev. A) PDF | HTML 2024年 3月 18日
Technical article Building multicamera vision perception systems for ADAS domain controllers with integrated processors PDF | HTML 2024年 1月 5日
Technical article How to deliver current beyond 100 A to an ADAS processor PDF | HTML 2024年 1月 4日
Functional safety information J721E, J721S2, J7200, J784S4 MCAL TUV Certification 2023年 12月 22日
Application note Jacinto7 HS Device Customer Return Process PDF | HTML 2023年 11月 16日
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. C) 2023年 9月 11日
White paper 以高度整合處理器設計高效邊緣 AI 系統 (Rev. A) PDF | HTML 2023年 4月 19日
User guide Powering Jacinto 7 SoC For Isolated Power Groups With TPS6594133A-Q1 + Dual HCPS PDF | HTML 2023年 3月 1日
Application note UART Log Debug System on Jacinto 7 SoC PDF | HTML 2023年 1月 9日
User guide Jacinto Processors TDA4AP/TDA4VP/TDA4AH/TDA4VH EVM Users Guide PDF | HTML 2022年 12月 2日
Functional safety information Jacinto™ 7 Safety Product Overview PDF | HTML 2022年 8月 15日
Application note Dual-TDA4x System Solution PDF | HTML 2022年 4月 29日
Application note SPI Enablement & Validation on TDA4 Family PDF | HTML 2022年 4月 5日
Technical article How are sensors and processors creating more intelligent and autonomous robots? PDF | HTML 2022年 3月 29日
Technical article How to simplify your embedded edge AI application development PDF | HTML 2022年 1月 28日
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 2022年 1月 10日
Application note TDA4 Flashing Techniques PDF | HTML 2021年 7月 8日
White paper Security Enablers on Jacinto™ 7 Processors 2021年 1月 4日
White paper Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors 2020年 10月 22日
Application note OSPI Tuning Procedure PDF | HTML 2020年 7月 8日

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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-J784S4 — Linux® SDK for TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1

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產品
Arm 式處理器
TDA4AP-Q1 — 用於具有 Arm® Cortex®-A72、AI 和視訊編碼器的 L2、L3 領域控制器的車用分析 SoC TDA4VP-Q1 — 用於具有 Arm® Cortex®-A72、圖形、AI 和視訊協同處理器的 L2、L3 領域控制器的車用 SoC TDA4AH-Q1 — 用於具有 AI 和視訊編碼器的感測器融合、L2、L3 領域控制器的車用分析 SoC TDA4VH-Q1 — 用於具有圖形、AI 和視訊協同處理器的感測器融合、L2、L3 領域控制器的車用 SoC
硬體開發
開發板
J784S4XEVM — TDA4AP、TDA4VP、TDA4AH 與 TDA4VH 評估模組
下載選項
軟體開發套件 (SDK)

PROCESSOR-SDK-QNX-J784S4 — QNX SDK for TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1

The J784S4 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TTDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1 system-on-a-chip (SoCs) (...)

支援產品和硬體

支援產品和硬體

產品
Arm 式處理器
TDA4AP-Q1 — 用於具有 Arm® Cortex®-A72、AI 和視訊編碼器的 L2、L3 領域控制器的車用分析 SoC TDA4VP-Q1 — 用於具有 Arm® Cortex®-A72、圖形、AI 和視訊協同處理器的 L2、L3 領域控制器的車用 SoC TDA4AH-Q1 — 用於具有 AI 和視訊編碼器的感測器融合、L2、L3 領域控制器的車用分析 SoC TDA4VH-Q1 — 用於具有圖形、AI 和視訊協同處理器的感測器融合、L2、L3 領域控制器的車用 SoC
硬體開發
開發板
J784S4XEVM — TDA4AP、TDA4VP、TDA4AH 與 TDA4VH 評估模組
下載選項
軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-J784S4 — RTOS SDK for TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1

The J784S4 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TTDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1 system-on-a-chip (SoCs) (...)

支援產品和硬體

支援產品和硬體

產品
Arm 式處理器
TDA4AH-Q1 — 用於具有 AI 和視訊編碼器的感測器融合、L2、L3 領域控制器的車用分析 SoC TDA4VH-Q1 — 用於具有圖形、AI 和視訊協同處理器的感測器融合、L2、L3 領域控制器的車用 SoC TDA4AP-Q1 — 用於具有 Arm® Cortex®-A72、AI 和視訊編碼器的 L2、L3 領域控制器的車用分析 SoC TDA4VP-Q1 — 用於具有 Arm® Cortex®-A72、圖形、AI 和視訊協同處理器的 L2、L3 領域控制器的車用 SoC
硬體開發
開發板
J784S4XEVM — TDA4AP、TDA4VP、TDA4AH 與 TDA4VH 評估模組
下載選項
應用軟體及架構

SV-3P-MULTIVISION — MultiVision - STRADVISION 汽車感知軟體

MultiVision 採用前置、後置、側面和環視 (魚眼) 攝影機的組合，可在公共道路和停車場環境中提供全面的車輛周圍物體偵測。MultiVision 支援 L2+ 或更高等級的 ADAS，以及跨各種操作設計領域 (ODD) 的自動駕駛功能。
從：Stradvision
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應用軟體及架構

SV-3P-SURROUNDVISION — SurroundVision - STRADVISION 汽車感知軟體

SurroundVision 會偵測車輛周圍的各種物體，包括車輛、行人、停車格和路緣，以環景攝影機影像作為輸入。透過其高準度的預警輸出，使用者可開發安全功能，例如盲區監控系統和自動停車輔助功能，即使在條件嚴苛的情境下也能發揮作用。
從：Stradvision
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IDE、配置、編譯器或偵錯程式

C7000-CGT — C7000 代碼產生工具 - 編譯器

The TI C7000 C/C++ Compiler Tools support development of applications for TI C7000 Digital Signal Processor cores.

Code Composer Studio is the Integrated Development Environment (IDE) for TI embedded devices.  If you are looking to develop on a TI embedded device it is recommended to start (...)
使用指南: PDF | HTML
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

支援產品和硬體

支援產品和硬體

此設計資源支援此類別中多數產品。

檢查產品詳細資料頁面以確認支援。
啟動 下載選項
IDE、配置、編譯器或偵錯程式

DDR-CONFIG-J784S4 — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
支援產品和硬體

支援產品和硬體

產品
Arm 式處理器
TDA4AP-Q1 — 用於具有 Arm® Cortex®-A72、AI 和視訊編碼器的 L2、L3 領域控制器的車用分析 SoC TDA4VP-Q1 — 用於具有 Arm® Cortex®-A72、圖形、AI 和視訊協同處理器的 L2、L3 領域控制器的車用 SoC TDA4AH-Q1 — 用於具有 AI 和視訊編碼器的感測器融合、L2、L3 領域控制器的車用分析 SoC TDA4VH-Q1 — 用於具有圖形、AI 和視訊協同處理器的感測器融合、L2、L3 領域控制器的車用 SoC AM69 — 具有圖形、PCIe Gen 3、乙太網路、USB 3.0 的通用八核心 64 位元 Arm Cortex-A72 AM69A — 適用 1-12 台攝影機、自主行動機器人、機器視覺、行動 DVR、AI 運算盒的 32 TOPS 視覺 SoC
硬體開發
開發板
SK-AM69 — 適用於視覺 AI 與通用處理器的 AM69 和 AM69A 入門套件
啟動
IDE、配置、編譯器或偵錯程式

SAFETI_CQKIT — 安全編譯器資格套件

The Safety Compiler Qualification Kit was developed to assist customers in qualifying their use of the TI ARM, C6000, C7000 or C2000/CLA C/C++ Compiler to functional safety standards such as IEC 61508 and ISO 26262.

The Safety Compiler Qualification Kit:

  • is free of charge for TI customers
  • does (...)
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IDE、配置、編譯器或偵錯程式

SYSCONFIG — 系統配置工具

SysConfig 是一款配置工具，專門設計用來簡化硬體與軟體配置挑戰，進而加速軟體開發。

SysConfig 是 Code Composer Studio™ 整合式開發環境的一部分，也是一個獨立式應用。此外，您也可造訪 TI開發人員區在雲端執行 SysConfig。

SysConfig 提供直覺式圖形使用者介面，可用於配置針腳、周邊設備、無線電、軟體堆疊、RTOS、時脈樹和其他元件。SysConfig 會自動偵測、找出並解決衝突，以加速軟體開發。

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作業系統 (OS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino RTOS

QNX Neutrino® 即時作業系統 (RTOS) 是一款功能完整且穩固的 RTOS，專為實現適用於汽車、醫療、運輸、軍事和工業嵌入式系統的新一代產品而設計。微核心設計與模組化架構，能讓客戶以低整體擁有成本打造高度最佳化且可靠的系統。
從：QNX Software Systems
造訪合作夥伴網站
支援軟體

EXLFR-3P-ESYNC-OTA — 適用於軟體定義車輛的 Excelfore esync OTA 無線更新

Experience the future of the connected SDV starting with full vehicle OTA from Excelfore. The standardized and structured eSync pipeline securely scales to reach all the ECUs and smart sensors in the car, with the flexibility to cover any in-vehicle network topology or system architecture.
eSync (...)
從：ExcelFore
造訪合作夥伴網站
支援軟體

EXLFR-3P-TSN — 適用於重要安全通訊的 ExelFore 的時效性網路 (TSN) 汽車路徑

軟體定義車輛 (SDV) 需要高性能網路、IP 定址和安全性，這些可透過乙太網路提供，但無法透過 CAN 提供。汽車應用也需要確保重要安全系統的延遲、頻寬和備援，這些是基本乙太網路無法提供的，但是 TSN 增加了這些功能。Excelfore 的 AVB/TSN 已通過 AVNU 認證。
乙太網路技術能以具成本效益的方式，將車內頻寬從 10MB 分支擴充至 10GB 以上。它還提供動態網路切換、網路安全性，而且能夠從雲端連線裝置。Excelfore 的 SOME/IP、DoIP、RTP、RTCP 和 UDS 通訊協定可將傳統系統帶入 SDV 時代，無縫整合至乙太網路骨幹，為 CAN (...)
從：ExcelFore
造訪合作夥伴網站
支援軟體

PAI-3P-PHANTOMVISION — 適用 ADAS 汽車應用且在 Jacinto 處理器上執行的 Phantom AI 視覺軟體

PhantomVision™ is a scalable, flexible and reliable deep learning based computer vision solution that provides a comprehensive suite of Euro NCAP compliant ADAS features. It is a visual perception engine that enables a single or multiple cameras to autonomously recognize road objects and (...)
從：Phantom AI
造訪合作夥伴網站
模擬型號

AM69 TDA4VH TDA4AH TDA4VP TDA4AP Thermal Model (Rev. A)

SPRM843A.ZIP (0 KB) - Thermal Model
下載
模擬型號

AM69A,TDA4VH-Q1,TDA4AH-Q1,TDA4VP-Q1,TDA4AP-Q1 BSDL MODEL

SPRM840.ZIP (18 KB) - BSDL Model
下載
模擬型號

IBIS Model for AM69 TDA4VH TDA4AH TDA4VP TDA4AP

SPRM836.ZIP (1497 KB) - IBIS Model
下載
封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (ALY) 1414 Ultra Librarian
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