THS0842
- Dual Simultaneous Sample and Hold Inputs
- Differential or Single-Ended Analog Inputs
- 8-Bit Resolution 40 MSPS Sampling Analog-to-Digital Converter (ADC)
- Single or Dual Parallel Bus Output
- Low Power Consumption: 275 mW Typ Using External References
- Wide Analog Input Bandwidth: 600 MHz Typ
- 3.3 V Single-Supply Operation
- 3.3 V TTL/CMOS-Compatible Digital I/O
- Internal or External Bottom and Top Reference Voltages
- Adjustable Reference Input Range
- Power-Down (Standby) Mode
- 48-Pin Thin Quad Flat Pack (TQFP) Package
- Applications
- Digital Communications (Baseband Sampling)
- Cable Modems
- Set Top Boxes
- Test Instruments
The THS0842 is a dual 8-bit 40 MSPS high-speed A/D converter. It alternately converts each analog input signal into 8-bit binary-coded digital words up to a maximum sampling rate of 40 MSPS with an 80 MHz clock. All digital inputs and outputs are 3.3 V TTL/CMOS-compatible.
Thanks to an innovative single-pipeline architecture implemented in a CMOS process and the 3.3 V supply, the device consumes very little power. In order to provide maximum flexibility, both bottom and top voltage references can be set from user supplied voltages. Alternately, if no external references are available, on-chip references can be used which are also made available externally. The full-scale range is 1 Vpp, depending on the analog supply voltage. If external references are available, the internal references can be powered down independently from the rest of the chip, resulting in an even greater power saving.
The device is specifically suited for the baseband sampling of wireless local loop (WLL) communication, cable modems, set top boxes (STBs), and test instruments.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | Dual-Input, 8-Bit, 40 MSPS, Low-Power ADC w/ Single or Dual Parallel Bus Output datasheet (Rev. A) | 2000年 8月 10日 | |
White paper | Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) | PDF | HTML | 2024年 4月 30日 | |
Application note | CDCE62005 as Clock Solution for High-Speed ADCs | 2008年 9月 4日 | ||
Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008年 6月 8日 | ||
Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008年 6月 2日 | ||
Application note | Noise Analysis for High Speed Op Amps (Rev. A) | 2005年 1月 17日 | ||
EVM User's guide | THS0842 EVM User's Guide (Rev. C) | 2000年 9月 28日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
TQFP (PFB) | 48 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點