TLC555-Q1
- AEC-Q100 qualified for automotive applications:
- Temperature grade 1: –40°C to +125°C, TA
- Functional Safety-Capable
- Very-low power consumption
- 1mW (typical) at VDD = 5V
- Capable of operation in astable mode
- CMOS output capable of swinging rail to rail
- High-output-current capability
- Sink 100mA (typical)
- Source 10mA (typical)
- Output fully compatible with CMOS, TTL, and MOS
- Low supply current reduces spikes during output transitions
- Single-supply operation from 2V to 15V
- Temperature range: –40°C to +125°C
- Functionally interchangeable with the NE555; has same pinout
The TLC555-Q1 is a monolithic timing circuit fabricated using TI LinCMOS™ technology. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2MHz. As a result of the high input impedance, this device supports smaller timing capacitors than capacitors used by the NE555. Thus, more accurate time delays and oscillations are possible. Power consumption is low across the full power-supply voltage range.
Like the NE555, the TLC555-Q1 has a trigger level equal to approximately one-third of the supply voltage, and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by using the control voltage pin (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set, and the output goes high. If TRIG is greater than the trigger level and the threshold input (THRES) is greater than the threshold level, the flip-flop is reset and the output goes low. The reset input (RESET) can override all other inputs and is used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output goes low. Whenever the output is low, a low-impedance path is provided between the discharge pin (DISCH) and GND. Tie all unused inputs to an appropriate logic level to prevent false triggering.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | TLC555-Q1 Automotive LinCMOS™ Technology Timer datasheet (Rev. C) | PDF | HTML | 2024年 4月 17日 |
Functional safety information | TLC555-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA (Rev. A) | PDF | HTML | 2023年 3月 13日 | |
Technical article | Power Tips: Multiply your output voltage | PDF | HTML | 2016年 7月 20日 | |
Design guide | EMC Compatible Automotive LED Rear Lamp Sequential-Turn Animation Design Guide | 2016年 6月 2日 | ||
Application note | TLC555-Q1 Used as a Positive and Negative Charge Pump | 2016年 5月 25日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
TLC555 TINA-TI Astable Reference Design (Rev. B)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
SOIC (D) | 8 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。