產品詳細資料

Configuration 2:1 SPDT Number of channels 2 Power supply voltage - single (V) 12, 16, 20, 36, 44 Power supply voltage - dual (V) +/-10, +/-15, +/-18, +/-22, +/-5 Protocols Analog Ron (typ) (Ω) 8.3 CON (typ) (pF) 30 ON-state leakage current (max) (µA) 0.027 Supply current (typ) (µA) 26 Bandwidth (MHz) 220 Operating temperature range (°C) -40 to 125 Features 1.8-V compatible control inputs, Break-before-make, Fail-safe logic, Overvoltage protection, Powered-off protection Input/output continuous current (max) (mA) 126.5 Rating Catalog Drain supply voltage (max) (V) 44 Supply voltage (max) (V) 44 Negative rail supply voltage (max) (V) -22
Configuration 2:1 SPDT Number of channels 2 Power supply voltage - single (V) 12, 16, 20, 36, 44 Power supply voltage - dual (V) +/-10, +/-15, +/-18, +/-22, +/-5 Protocols Analog Ron (typ) (Ω) 8.3 CON (typ) (pF) 30 ON-state leakage current (max) (µA) 0.027 Supply current (typ) (µA) 26 Bandwidth (MHz) 220 Operating temperature range (°C) -40 to 125 Features 1.8-V compatible control inputs, Break-before-make, Fail-safe logic, Overvoltage protection, Powered-off protection Input/output continuous current (max) (mA) 126.5 Rating Catalog Drain supply voltage (max) (V) 44 Supply voltage (max) (V) 44 Negative rail supply voltage (max) (V) -22
TSSOP (PW) 16 32 mm² 5 x 6.4
  • Wide supply voltage range:
    • Single supply: 8 V to 44 V
    • Dual supply: ±5 V to ±22 V
  • Integrated fault protection:
    • Overvoltage protection, source to supplies or source to drain: ±85 V
    • Overvoltage protection: ±60 V
    • Powered-off protection: ±60 V
    • Interrupt flags to indicate fault status
    • Output open circuited during fault
  • Latch-up immunity by device construction
  • 6 kV human body model (HBM) ESD rating
  • Low On-Resistance: 8.6 Ω typical
  • Flat On-Resistance: 10 mΩ typical
  • 1.8-V Logic capable
  • Failsafe logic: up to 44 V independent of supply

  • Industry-standard TSSOP and smaller WQFN packages
  • Wide supply voltage range:
    • Single supply: 8 V to 44 V
    • Dual supply: ±5 V to ±22 V
  • Integrated fault protection:
    • Overvoltage protection, source to supplies or source to drain: ±85 V
    • Overvoltage protection: ±60 V
    • Powered-off protection: ±60 V
    • Interrupt flags to indicate fault status
    • Output open circuited during fault
  • Latch-up immunity by device construction
  • 6 kV human body model (HBM) ESD rating
  • Low On-Resistance: 8.6 Ω typical
  • Flat On-Resistance: 10 mΩ typical
  • 1.8-V Logic capable
  • Failsafe logic: up to 44 V independent of supply

  • Industry-standard TSSOP and smaller WQFN packages

The TMUX7436F is a complementary metal-oxide semiconductor (CMOS) analog multiplexer with latch-up immunity in a dual channel, 2:1 configuration. The device works well with dual supplies (±5 V to ±22 V), a single supply (8 V to 44 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5  V). The overvoltage protection is available in powered and powered-off conditions, making the TMUX7436F device suitable for applications where power supply sequencing cannot be precisely controlled.

The device blocks fault voltages up to +60 V or −60 V relative to ground in powered and powered-off conditions. When no power supplies are present, the switch channels remain in the OFF state regardless of switch input conditions, and any control signal present on the logic pins is ignored. If the signal path input voltage on any Sx pin exceeds the supply voltage (VDD or VSS) by a threshold voltage (VT), then the channel turns OFF and the Sx pin becomes high impedance. The drain pin (Dx) is either pulled to the fault supply voltage that was exceeded or left floating depending on the DR control logic. The TMUX7436F device provides two active-low interrupt flags (FF and SF) to provide details of the fault and help system diagnostics. The FF flag indicates if any of the source inputs are experiencing a fault condition, while the SF flag is used to decode which specific inputs are experiencing a fault condition.

The TMUX7436F is a complementary metal-oxide semiconductor (CMOS) analog multiplexer with latch-up immunity in a dual channel, 2:1 configuration. The device works well with dual supplies (±5 V to ±22 V), a single supply (8 V to 44 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5  V). The overvoltage protection is available in powered and powered-off conditions, making the TMUX7436F device suitable for applications where power supply sequencing cannot be precisely controlled.

The device blocks fault voltages up to +60 V or −60 V relative to ground in powered and powered-off conditions. When no power supplies are present, the switch channels remain in the OFF state regardless of switch input conditions, and any control signal present on the logic pins is ignored. If the signal path input voltage on any Sx pin exceeds the supply voltage (VDD or VSS) by a threshold voltage (VT), then the channel turns OFF and the Sx pin becomes high impedance. The drain pin (Dx) is either pulled to the fault supply voltage that was exceeded or left floating depending on the DR control logic. The TMUX7436F device provides two active-low interrupt flags (FF and SF) to provide details of the fault and help system diagnostics. The FF flag indicates if any of the source inputs are experiencing a fault condition, while the SF flag is used to decode which specific inputs are experiencing a fault condition.

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類型 標題 日期
* Data sheet TMUX7436F ±60 V Fault-Protected, Dual 2:1 MultiplexerWith Latch-Up Immunity and 1.8 V Logic datasheet (Rev. A) PDF | HTML 2022年 11月 18日
Application brief How to Protect a Multi-Channel RTD System using Fault Protected Multiplexers (Rev. A) PDF | HTML 2024年 8月 8日
Application note Protecting and Maintaining Signal Integrity in PLC Systems (Rev. A) PDF | HTML 2024年 7月 22日

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介面轉接器

LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

使用指南: PDF
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介面轉接器

LEADLESS-ADAPTER1 — 用於測試 TI 的 6、8、10、12、14、16 和 20 針腳無引線封裝的表面貼裝至 DIP 接頭適配器

The EVM-LEADLESS1 board allows for quick testing and bread boarding of TI's common leadless packages.  The board has footprints to convert TI's DRC, DTP, DQE, RBW, RGY, RSE, RSV, RSW RTE, RTJ, RUK , RUC, RUG, RUM,RUT and YZP surface mount packages to 100mil DIP headers.
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模擬型號

TMUX7436F IBIS Model

SCDM304.ZIP (34 KB) - IBIS Model
封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (PW) 16 Ultra Librarian

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