計算工具
FET-INRUSH-SOA-CALC — FET SOA margin calculator for dvdt based startup
The design calculator allows user to estimate the FET SOA margin while starting up with dVdt based startup for inrush current control
TPS4810-Q1
- AEC-Q100 automotive qualified for automotive applications
- Device temperature grade 1: –40°C to +125°C ambient operating temperature range
- Functional Safety-Capable
- 3.5V to 80V input range (100V absolute maximum)
- Reverse input protection down to –65V
- Integrated 11V charge pump with 345µA capacity
- Low quiescent current, 35µA in operation
- Low 1.5µA shutdown current (EN/UVLO = Low)
- Two strong gate drivers (2A source and sink) for back to back MOSFET driving with separate control inputs (INP1, INP2)
- Adjustable short circuit protection (ISCP) using external Rsense or MOSFET VDS sensing with adjustable delay (TMR)
- High or low-side current sense configuration (CS_SEL)
- Fault indication (FLT) during short circuit fault, charge pump undervoltage, input undervoltage, and short-circuit comparator diagnosis (SCP_TEST)
- Adjustable input undervoltage lockout (UVLO)
- Pin-to-pin compatible with TPS1210-Q1
The TPS48100-Q1 is a 100V low IQ smart high side driver with protection and diagnostics. With wide operating voltage range of 3.5V–80V, the device is suitable for 12V, 24V, and 48V system designs. The device can withstand and protect the loads from negative supply voltages down to –65V.
It has two strong 2A (source and sink) gate drivers with separate control inputs (INP1, INP2) to drive back to back MOSFETs in common source configuration. Strong GATE driving enables power switching using parallel MOSFETs in high current system designs.
The device provides adjustable short-circuit protection. Auto-retry and latch-off fault behavior can be configured. Current sensing can be done either by an external sense resistor or by MOSFET VDS sensing. High side or low side current sense resistor configuration is possible by using CS_SEL pin input. The device also features diagnosis of the internal short circuit comparator using external control on SCP_TEST input.
A low quiescent current (35µA, typical) in operation enables always ON system designs. Quiescent current reduces to 1.5µA (typical) with EN/UVLO low.
The TPS48100-Q1 is available in a 19-pin VSSOP package.
技術文件
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檢視所有 3 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | TPS4810-Q1 100V Automotive Low IQ , Back-to-Back MOSFET Smart High Side Driver With Short-Circuit Protection and Diagnostics datasheet | PDF | HTML | 2024年 1月 29日 |
| EVM User's guide | TPS4810Q1EVM, TPS4810-Q1 Evaluation Module for Smart High-Side Driver | PDF | HTML | 2023年 10月 11日 | |
| Certificate | TPS4810Q1EVM EU Declaration of Conformity (DoC) | 2023年 5月 22日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
TPS4810Q1EVM — 適用於具有短路保護的 3-V 至 80-V 低 IQ 雙高壓側驅動器的 TPS4810-Q1 評估模組
TPS4810-Q1 評估模組 (EVM) 是用於評估 TPS4810-Q1 驅動器參考電路的平台。TPS4810-Q1 是 3-V 至 80-V 高壓側控制器，具有兩個含獨立控制輸入 (INP1、INP2) 的強 2-A 閘極驅動器，可驅動採用共源配置的背對背金屬氧化半導體場效電晶體 (MOSFET)。TPS4810-Q1 提供具備可配置自動重試和閉鎖故障行為的可調整短路防護。
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VSSOP (DGX) | 19 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。