產品詳細資料

Current consumption (mA) 53 Frequency (min) (MHz) 1 Frequency (max) (MHz) 6000 Gain (typ) (dB) 20 Impedance match (Ω) 50 Noise figure (typ) (dB) 3.2 Number of channels 1 Operating temperature range (°C) -40 to 85 Output enable Yes OIP3 (typ) (dBm) 28 P1dB (typ) (dBm) 16.5 Type RF Gain Block Rating Catalog Power-down current Yes
Current consumption (mA) 53 Frequency (min) (MHz) 1 Frequency (max) (MHz) 6000 Gain (typ) (dB) 20 Impedance match (Ω) 50 Noise figure (typ) (dB) 3.2 Number of channels 1 Operating temperature range (°C) -40 to 85 Output enable Yes OIP3 (typ) (dBm) 28 P1dB (typ) (dBm) 16.5 Type RF Gain Block Rating Catalog Power-down current Yes
WSON (DSG) 8 4 mm² 2 x 2
  • 1 MHz – 6000 MHz
  • Gain: 19.5 dB
  • Noise Figure: 3.25 dB
  • Output P1dB: 16.5 dBm at 2000 MHz
  • Output IP3: 28 dBm at 2000 MHz
  • Power Down Mode
  • Single Supply: 3.3 V
  • Stabilized Performance Over Temperature
  • Unconditionally Stable
  • Robust ESD: >1 kV HBM; >1 kV CDM
  • 1 MHz – 6000 MHz
  • Gain: 19.5 dB
  • Noise Figure: 3.25 dB
  • Output P1dB: 16.5 dBm at 2000 MHz
  • Output IP3: 28 dBm at 2000 MHz
  • Power Down Mode
  • Single Supply: 3.3 V
  • Stabilized Performance Over Temperature
  • Unconditionally Stable
  • Robust ESD: >1 kV HBM; >1 kV CDM

The TRF37D73 is packaged in a 2.00mm × 2.00mm WSON with a power down pin feature making it ideal for applications where space and low power modes are critical.

The TRF37D73 is designed for ease of use. For maximum flexibility, this family of parts uses a common 3.3 V supply and consumes 53 mA. In addition, this family was designed with an active bias circuit that provides a stable and predictable bias current over process, temperature and voltage variations. For gain and linearity budgets the device was designed to provide a flat gain response and excellent OIP3 out to 6000 MHz. For space constrained applications, this family is internally matched to 50 Ω, which simplifies ease of use and minimizes needed PCB area.

For all available packages, see the orderable addendum at the end of the datasheet.

The TRF37D73 is packaged in a 2.00mm × 2.00mm WSON with a power down pin feature making it ideal for applications where space and low power modes are critical.

The TRF37D73 is designed for ease of use. For maximum flexibility, this family of parts uses a common 3.3 V supply and consumes 53 mA. In addition, this family was designed with an active bias circuit that provides a stable and predictable bias current over process, temperature and voltage variations. For gain and linearity budgets the device was designed to provide a flat gain response and excellent OIP3 out to 6000 MHz. For space constrained applications, this family is internally matched to 50 Ω, which simplifies ease of use and minimizes needed PCB area.

For all available packages, see the orderable addendum at the end of the datasheet.

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類型 標題 日期
* Data sheet TRF37D73 1-6000 MHz RF Gain Block datasheet PDF | HTML 2014年 5月 30日
User guide TRF37x73 and TRF37x75 EVM User’s Guide (Rev. A) PDF | HTML 2021年 5月 4日
User guide TRF37x73 and TRF37x75 EVM User’s Guide 2014年 3月 26日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TRF37D73EVM — TRF37D73 評估模組

The TRF37X73EVM evaluation module is intended for the evaluation of the TRF37x73 RF gain blocks.  The gain blocks come in multiple gain versions.  See each respective product datasheet to be sure you are ordering the correct gain block for the gain and frequency of intended operation.

使用指南: PDF | HTML
TI.com 無法提供
模擬型號

TRF37D73 ADS2014 Model

SLAJ007.ZIP (47 KB) - Spice Model
模擬型號

TRF37D73 S-Parameter Model

SLAM234.ZIP (44 KB) - S-Parameter Model
模擬型號

TRF37D73 TINA-TI Reference Design

SLAM263.TSC (287 KB) - TINA-TI Reference Design
模擬型號

TRF37D73 TINA-TI Spice Model

SLAM262.ZIP (3 KB) - TINA-TI Spice Model
CAD/CAE 符號

Low Frequency S-Parameters, 1M - 200M 4.7uH

SLAR109.ZIP (28 KB)
CAD/CAE 符號

Low Frequency S-Parameters, 1M - 400M 680nH

SLAR110.ZIP (55 KB)
參考設計

TIDA-00347 — 低頻率射頻放大器參考設計

Wideband RF amplifiers require external coupling capacitors and an RF choke to supply bias to the output transistor collector.  As the frequency of operation is reduced, the choice of these components must be modified to maintain proper gain and linearity in the device.  This design (...)
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
WSON (DSG) 8 Ultra Librarian

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