封裝資訊
| 封裝 | 針腳 NFBGA (ZBA) | 48 |
| 操作溫度範圍 (°C) -40 to 85 |
| 包裝數量 | 運送業者 3,000 | LARGE T&R |
TS3DDR4000 的特色
- Wide VDD Range: 2.375 V – 3.6 V
- High Bandwidth: 5.6 GHz Typical (single-ended); 6.0 GHz Typical (differential)
- Low Switch On-Resistance (RON): 8 Ω Typical
- Low Bit-to-Bit Skew: 3ps Typical; 6ps Max across All Channels
- Low Crosstalk: –34 dB Typical at 1067 MHz
- Low Operating Current: 40 µA Typical
- Low-Power Mode with Low Current Consumption: 2 µA Typical
- IOFF Protection Prevents Current Leakage in Powered Down State (VDD = 0 V)
- Supports POD_12, SSTL_12, SSTL_15 and SSTL_18 Signaling
- ESD Performance:
- 3-kV Human Body Model (A114B, Class II)
- 1-kV Charged Device Model (C101)
- 8 mm x 3 mm 48-balls 0.65-mm Pitch ZBA Package
TS3DDR4000 的說明
The TS3DDR4000 is 1:2 or 2:1 high speed DDR2/DDR3/DDR4 switch that offers 12-bit wide bus switching. The A port can be switched to the B or C port for all bits simultaneously. Designed for operation in DDR2, DDR3 and DDR4 memory bus systems, the TS3DDR4000 uses a proprietary architecture that delivers high bandwidth (single-ended –3dB bandwidth at 5.6 GHz), low insertion loss at low frequency, and very low propagation delay. The TS3DDR4000 is 1.8 V logic compatible, and all switches are bi-directional for added design flexibility. The TS3DDR4000 also offers a low-power mode, in which all channels become high-Z and the device consumes minimal power.