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TS5A6542

現行

具輸入邏輯轉換的 0.75-Ω 低導通電阻、5-V、2:1 (SPDT)、1 通道類比開關

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產品規格表

TS5A6542

現行
產品規格表 立即訂購

產品詳細資料

Configuration 2:1 SPDT Number of channels 1 Power supply voltage - single (V) 2.5, 3.3, 5 Protocols Analog Ron (typ) (Ω) 0.5 CON (typ) (pF) 133 ON-state leakage current (max) (µA) 0.2 Supply current (typ) (µA) 0.01 Bandwidth (MHz) 43 Operating temperature range (°C) -40 to 85 Features 1.8-V compatible control inputs, Break-before-make Input/output continuous current (max) (mA) 450 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
Configuration 2:1 SPDT Number of channels 1 Power supply voltage - single (V) 2.5, 3.3, 5 Protocols Analog Ron (typ) (Ω) 0.5 CON (typ) (pF) 133 ON-state leakage current (max) (µA) 0.2 Supply current (typ) (µA) 0.01 Bandwidth (MHz) 43 Operating temperature range (°C) -40 to 85 Features 1.8-V compatible control inputs, Break-before-make Input/output continuous current (max) (mA) 450 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25
  • Specified Break-Before-Make Switching
  • Low ON-State Resistance (0.75 Max)
  • Control Inputs Referenced to VIO
  • Low Charge Injection
  • Excellent ON-State Resistance Matching
  • Low Total Harmonic Distortion (THD)
  • 2.25-V to 5.5-V Power Supply (V+)
  • 1.65-V to 1.95-V Logic Supply (VIO)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 4000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
    • 400-V Machine Model (A115-A)
  • COM Port to GND
    • 8000-V Human-Body Model
      (A114-B, Class II)
    • ±15-kV Contact Discharge (IEC 61000-4-2)
  • APPLICATIONS
    • Cell Phones
    • PDAs
    • Portable Instrumentation
  • Specified Break-Before-Make Switching
  • Low ON-State Resistance (0.75 Max)
  • Control Inputs Referenced to VIO
  • Low Charge Injection
  • Excellent ON-State Resistance Matching
  • Low Total Harmonic Distortion (THD)
  • 2.25-V to 5.5-V Power Supply (V+)
  • 1.65-V to 1.95-V Logic Supply (VIO)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 4000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
    • 400-V Machine Model (A115-A)
  • COM Port to GND
    • 8000-V Human-Body Model
      (A114-B, Class II)
    • ±15-kV Contact Discharge (IEC 61000-4-2)
  • APPLICATIONS
    • Cell Phones
    • PDAs
    • Portable Instrumentation

The TS5A6542 is a single-pole double-throw (SPDT) analog switch that is designed to operate from 2.25 V to 5.5 V. The device offers a low ON-state resistance with an excellent channel-to-channel ON-state resistance matching, and the break-before-make feature to prevent signal distorion during the transferring of a signal from one path to another. The device has excellent total harmonic distortion (THD) performance and consumes very low power. These features make this device suitable for portable audio applications.

The TS5A6542 has a separate logic supply pin (VIO) that is characterized to operate from 1.65 V to 1.95 V. VIO powers the control circuitry, which allows the TS5A6542 to be controlled by 1.8-V signals.

The TS5A6542 is a single-pole double-throw (SPDT) analog switch that is designed to operate from 2.25 V to 5.5 V. The device offers a low ON-state resistance with an excellent channel-to-channel ON-state resistance matching, and the break-before-make feature to prevent signal distorion during the transferring of a signal from one path to another. The device has excellent total harmonic distortion (THD) performance and consumes very low power. These features make this device suitable for portable audio applications.

The TS5A6542 has a separate logic supply pin (VIO) that is characterized to operate from 1.65 V to 1.95 V. VIO powers the control circuitry, which allows the TS5A6542 to be controlled by 1.8-V signals.
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類型 標題 日期
* Data sheet TS5A6542 0.75-Ohm SPDT Analog Switch With Input Logic Translation datasheet (Rev. C) 2009年 12月 11日
Application note High-Efficiency Charging for TWS Using a 2-Pin Interface Application Report (Rev. A) PDF | HTML 2023年 5月 16日
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022年 6月 2日
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021年 12月 1日
Application note Preventing Excess Power Consumption on Analog Switches 2008年 7月 3日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日

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介面轉接器

LEADLESS-ADAPTER1 — 用於測試 TI 的 6、8、10、12、14、16 和 20 針腳無引線封裝的表面貼裝至 DIP 接頭適配器

The EVM-LEADLESS1 board allows for quick testing and bread boarding of TI's common leadless packages.  The board has footprints to convert TI's DRC, DTP, DQE, RBW, RGY, RSE, RSV, RSW RTE, RTJ, RUK , RUC, RUG, RUM,RUT and YZP surface mount packages to 100mil DIP headers.
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模擬型號

HSPICE MODEL OF TS5A6542

SCEJ226.ZIP (90 KB) - HSpice Model
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模擬型號

TS5A6542 IBIS Model

SCEM514.ZIP (67 KB) - IBIS Model
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