產品詳細資料

Technology family TXB Applications GPIO Bits (#) 8 Data rate (max) (Mbps) 100 High input voltage (min) (V) 0.78 High input voltage (max) (V) 5.5 Vout (min) (V) 1.2 Vout (max) (V) 5.5 IOH (max) (mA) -0.02 IOL (max) (mA) 0.02 Supply current (max) (µA) 10 Features Edge rate accelerator, Integrated pullup resistors, Output enable, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type 3-State, CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family TXB Applications GPIO Bits (#) 8 Data rate (max) (Mbps) 100 High input voltage (min) (V) 0.78 High input voltage (max) (V) 5.5 Vout (min) (V) 1.2 Vout (max) (V) 5.5 IOH (max) (mA) -0.02 IOL (max) (mA) 0.02 Supply current (max) (µA) 10 Features Edge rate accelerator, Integrated pullup resistors, Output enable, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type 3-State, CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YZP) 20 6.1875 mm² 2.25 x 2.75 NFBGA (NME) 20 7.5 mm² 2.5 x 3 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4 USON (DQS) 20 8 mm² 4 x 2 VQFN (RGY) 20 15.75 mm² 4.5 x 3.5
  • 1.2 V to 3.6 V on A Port and 1.65 V to 5.5 V on B Port (VCCA ≤ VCCB)
  • VCC Isolation Feature – If Either VCC Input Is at GND, All Outputs Are in the High-Impedance State
  • OE Input Circuit Referenced to VCCA
  • Low Power Consumption, 4-µA Max ICC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • A Port
      • 2000-V Human-Body Model (A114-B)
      • 1000-V Charged-Device Model (C101)
    • B Port
      • ±15-kV Human-Body Model (A114-B)
      • ±8-kV Human-Body Model (A114-B) (YZP Package Only)
      • 1000-V Charged-Device Model (C101)
  • 1.2 V to 3.6 V on A Port and 1.65 V to 5.5 V on B Port (VCCA ≤ VCCB)
  • VCC Isolation Feature – If Either VCC Input Is at GND, All Outputs Are in the High-Impedance State
  • OE Input Circuit Referenced to VCCA
  • Low Power Consumption, 4-µA Max ICC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • A Port
      • 2000-V Human-Body Model (A114-B)
      • 1000-V Charged-Device Model (C101)
    • B Port
      • ±15-kV Human-Body Model (A114-B)
      • ±8-kV Human-Body Model (A114-B) (YZP Package Only)
      • 1000-V Charged-Device Model (C101)

This 8-bit noninverting translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. VCCA should not exceed VCCB.

When the output-enable (OE) input is low, all outputs are placed in the high-impedance state.

The TXB0108 is designed so that the OE input circuit is supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power-up or power-down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

This 8-bit noninverting translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. VCCA should not exceed VCCB.

When the output-enable (OE) input is low, all outputs are placed in the high-impedance state.

The TXB0108 is designed so that the OE input circuit is supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power-up or power-down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

下載 觀看有字幕稿的影片 影片

您可能會感興趣的類似產品

open-in-new 比較替代產品
功能相同,但引腳輸出與所比較的裝置不同
TXB0104 現行 具自動方向感測和 +/-15-kV ESD 保護的 4 位元雙向電壓位準移位器 Same function for 4-channel voltage translator

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 12
類型 標題 日期
* Data sheet TXB0108 8-Bit Bidirectional Voltage-Level Translator with Auto-Direction Sensing and ±15-kV ESD Protection datasheet (Rev. H) PDF | HTML 2020年 8月 25日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
Application note Leveraging Edge Rate Accelerators with Auto-Sensing Level Shifters PDF | HTML 2023年 9月 29日
Application brief Future-Proofing Your Level Shifter Design with TI's Dual Footprint Packages PDF | HTML 2023年 9月 5日
Application note Do’s and Don’ts for TXB and TXS Voltage Level-Shifters with Edge Rate Accelerato PDF | HTML 2023年 6月 28日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Application note Effects of pullup and pulldown resistors on TXS and TXB devices (Rev. A) 2018年 3月 28日
Application note Factors Affecting VOL for TXS and LSF Auto-bidirectional Translation Devices 2017年 11月 19日
Application note Biasing Requirements for TXS, TXB, and LSF Auto-Bidirectional Translators 2017年 10月 30日
Application note A Guide to Voltage Translation With TXS-Type Translators 2010年 6月 29日
Application note A Guide to Voltage Translation With TXB-Type Translators 2010年 3月 3日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
TI.com 無法提供
開發板

14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組

14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM),設計用途可支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。

使用指南: PDF | HTML
TI.com 無法提供
開發板

LP-AM263 — AM263x Arm® 架構 MCU 通用型 LaunchPad™ 開發套件

LP AM263 為 AM263x 系列的 Sitara™ 高性能微控制器 (MCU) 的成本最佳化開發電路板。此電路板極適用於初始評估與原型,因為它提供標準化且使用方便的平台,可用於開發您的下一個應用程式。

LP AM263 配備了 Sitara AM2634 處理器及其他零組件,可讓使用者使用各種裝置介面,其中包括工業乙太網路 (IE)、標準乙太網路、快速序列介面 (FSI) 及其他功能,可用於輕鬆建立原型。AM2634 支援各種 IE 協定如 EtherCAT、EtherNet/IP 和 PROFINET®。

此延伸 LaunchPad™ XL 開發套件提供額外的 I/O (...)

使用指南: PDF | HTML
TI.com 無法提供
開發板

TXB-EVM — 1 至 8 位元 TXB 轉換器系列評估模組

This EVM is designed to support the TXB auto bidirectional families for single, dual, four and eight channel devices. The TXB devices belong to the auto bidirectional translation family with an operating voltage designed to level translation between 1.2V and 5.5 V.
使用指南: PDF | HTML
TI.com 無法提供
模擬型號

HSPICE Model for TXB0108 (Rev. A)

SCEJ242A.ZIP (101 KB) - HSpice Model
模擬型號

TXB0108 IBIS Model (Rev. G)

SCEM518G.ZIP (205 KB) - IBIS Model
參考設計

TIDA-060043 — 56G 重定時器 MCB QSFP-DD 參考設計

此參考設計展現 56G PAM-4 重定時器 DS560DF410 如何用於將主動式電力電纜應用中的高速訊號等化。此設計是模組相容電路板 (MCB),可將來自 QSFP-DD 連接器的訊號透過重定時器,以入口和出口方向傳送至 SMA 和 MXP 連接器。
Design guide: PDF
參考設計

TIDA-01435 — 適用於微波回程連線的高頻寬、零中頻參考設計

The TSW40RF82EVM reference design provides a platform to interface the DAC38RF82 with a high-performance modulator - the TRF370417EVM. The TRF370417EVM can modulate wideband signals at up to 6 GHz as would be typical for a microwave backhaul application. The TRF370417 device may be substituted for (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00352 — SDI 視訊聚合參考設計

This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is (...)
Test report: PDF
電路圖: PDF
參考設計

TIDA-00309 — DisplayPort 視訊 4:1 聚合參考設計

This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a (...)
Test report: PDF
電路圖: PDF
參考設計

TIDA-00269 — Gigabit 乙太網路鏈路聚合器參考設計

The Gigabit Ethernet Link Aggregator reference design features the TLK10081 device which is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems to reduce the number of physical links by multiplexing lower speed serial links into higher (...)
Test report: PDF
電路圖: PDF
參考設計

TIDA-00234 — 適用於具有兩個或多個 SFP+ 光學連接埠之系統的雙通道 XAUI 到 SFI 參考設計

The TIDA-00234 XAUI to SFI reference design is intended for Enterprise and Service Provider Networking applications like Ethernet Switches and Routers that implement multiple 10G Ethernet compliant Optical (SFP+) ports. This reference design features the TLK10232 device which is the most compact (...)
Test report: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
DSBGA (YZP) 20 Ultra Librarian
NFBGA (NME) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
USON (DQS) 20 Ultra Librarian
VQFN (RGY) 20 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片