TXB0108

現行

具自動方向感測和 +/-15-kV ESD 保護的 8 位元雙向電壓位準移位器

產品詳細資料

Technology family TXB Applications GPIO Bits (#) 8 Data rate (max) (Mbps) 100 High input voltage (min) (V) 0.78 High input voltage (max) (V) 5.5 Vout (min) (V) 1.2 Vout (max) (V) 5.5 IOH (max) (mA) -0.02 IOL (max) (mA) 0.02 Supply current (max) (µA) 10 Features Edge rate accelerator, Integrated pullup resistors, Output enable, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type 3-State, CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family TXB Applications GPIO Bits (#) 8 Data rate (max) (Mbps) 100 High input voltage (min) (V) 0.78 High input voltage (max) (V) 5.5 Vout (min) (V) 1.2 Vout (max) (V) 5.5 IOH (max) (mA) -0.02 IOL (max) (mA) 0.02 Supply current (max) (µA) 10 Features Edge rate accelerator, Integrated pullup resistors, Output enable, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type 3-State, CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YZP) 20 6.1875 mm² 2.25 x 2.75 NFBGA (NME) 20 7.5 mm² 2.5 x 3 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4 USON (DQS) 20 8 mm² 4 x 2 VFBGA (ZXY) 20 See data sheet VQFN (RGY) 20 15.75 mm² 4.5 x 3.5
  • 1.2 V to 3.6 V on A Port and 1.65 V to 5.5 V on B Port (VCCA ≤ VCCB)
  • VCC Isolation Feature – If Either VCC Input Is at GND, All Outputs Are in the High-Impedance State
  • OE Input Circuit Referenced to VCCA
  • Low Power Consumption, 4-µA Max ICC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • A Port
      • 2000-V Human-Body Model (A114-B)
      • 1000-V Charged-Device Model (C101)
    • B Port
      • ±15-kV Human-Body Model (A114-B)
      • ±8-kV Human-Body Model (A114-B) (YZP Package Only)
      • 1000-V Charged-Device Model (C101)
  • 1.2 V to 3.6 V on A Port and 1.65 V to 5.5 V on B Port (VCCA ≤ VCCB)
  • VCC Isolation Feature – If Either VCC Input Is at GND, All Outputs Are in the High-Impedance State
  • OE Input Circuit Referenced to VCCA
  • Low Power Consumption, 4-µA Max ICC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • A Port
      • 2000-V Human-Body Model (A114-B)
      • 1000-V Charged-Device Model (C101)
    • B Port
      • ±15-kV Human-Body Model (A114-B)
      • ±8-kV Human-Body Model (A114-B) (YZP Package Only)
      • 1000-V Charged-Device Model (C101)

This 8-bit noninverting translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. VCCA should not exceed VCCB.

When the output-enable (OE) input is low, all outputs are placed in the high-impedance state.

The TXB0108 is designed so that the OE input circuit is supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power-up or power-down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

This 8-bit noninverting translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. VCCA should not exceed VCCB.

When the output-enable (OE) input is low, all outputs are placed in the high-impedance state.

The TXB0108 is designed so that the OE input circuit is supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power-up or power-down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

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TXB0104 現行 具自動方向感測和 +/-15-kV ESD 保護的 4 位元雙向電壓位準移位器 Same function for 4-channel voltage translator

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類型 標題 日期
* Data sheet TXB0108 8-Bit Bidirectional Voltage-Level Translator with Auto-Direction Sensing and ±15-kV ESD Protection datasheet (Rev. H) PDF | HTML 2020年 8月 25日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
Application note Leveraging Edge Rate Accelerators with Auto-Sensing Level Shifters PDF | HTML 2023年 9月 29日
Application brief Future-Proofing Your Level Shifter Design with TI's Dual Footprint Packages PDF | HTML 2023年 9月 5日
Application note Do’s and Don’ts for TXB and TXS Voltage Level-Shifters with Edge Rate Accelerato PDF | HTML 2023年 6月 28日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Application note Effects of pullup and pulldown resistors on TXS and TXB devices (Rev. A) 2018年 3月 28日
Application note Factors Affecting VOL for TXS and LSF Auto-bidirectional Translation Devices 2017年 11月 19日
Application note Biasing Requirements for TXS, TXB, and LSF Auto-Bidirectional Translators 2017年 10月 30日
Application note A Guide to Voltage Translation With TXS-Type Translators 2010年 6月 29日
Application note A Guide to Voltage Translation With TXB-Type Translators 2010年 3月 3日

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模擬型號

HSPICE Model for TXB0108 (Rev. A)

SCEJ242A.ZIP (101 KB) - HSpice Model
模擬型號

TXB0108 IBIS Model (Rev. G)

SCEM518G.ZIP (205 KB) - IBIS Model
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
DSBGA (YZP) 20 Ultra Librarian
NFBGA (NME) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
USON (DQS) 20 Ultra Librarian
VFBGA (ZXY) 20 Ultra Librarian
VQFN (RGY) 20 Ultra Librarian

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