SBAA436 March 2021 REF34-Q1 , REF3425 , REF3425-EP , REF3430 , REF3430-EP , REF3433 , REF3433-EP , REF3440 , REF3440-EP , REF3450 , REF4132 , REF4132-Q1 , REF5010 , REF5020 , REF5020-EP , REF5020A-Q1 , REF5025 , REF5025-EP , REF5025-HT , REF5025A-Q1 , REF5030 , REF5030A-Q1 , REF5040 , REF5040-EP , REF5040A-Q1 , REF5045 , REF5045A-Q1 , REF5050 , REF5050-EP , REF5050A-Q1 , REF6125 , REF6133 , REF6141 , REF6145 , REF6150 , REF6225 , REF6230 , REF6233 , REF6241 , REF6245 , REF6250 , REF70
Multiple applications demand that the systems will operate without periodic calibration for long periods of time. In these situations then LTD can be one of the dominant contributors in the error budget. REF34-Q1 Gain Error Breakdown illustrates a comparison between errors of the REF34-Q1. For more details on all error sources of a voltage reference, see the Voltage Reference Design Tips For Data Converters Application Note.
| Parameter | Error (ppm) | Source | Notes | Error Reduction Method | % of Total (No Calibration) | % of Total (With Initial Calibration) |
|---|---|---|---|---|---|---|
| Initial accuracy | 500 | Data sheet maximum value | Calibration at 25°C | 27.4% | 0% | |
| Solder shift | 100 | Data sheet typical value | Calibration at 25°C | 5.49% | 0% | |
| Temperature drift | 990 | Data sheet maximum value | 6ppm/C × (125 – (-40))°C = 990 ppm | Calibration across temperature | 54.3% | 80.9% |
| Long-Term Drift | 234 | Data sheet typical value | Conservative estimate based on 10 yr value | LTD shift = 25 × sqrt(hr/1000) | 12.8% | 19.1% |
In this example the LTD is the third highest error at 234 ppm without calibration in situations where the life cycle of the system is very long due to the low LTD of the REF34 in SOT23-3. Initial calibration can be implemented in the signal chain which reduces the error of the voltage reference at the temperature it was calibrated at. In REF34-Q1 Gain Error Breakdown the initial calibration reduces the error that exists at 25°C and post solder shift. LTD becomes the second highest error if there is initial calibration. The 10 year LTD value was calculated using the typical value using an equation which results with a conservative value.
The primary reason for change in output voltage over time for the same temperature and electrical conditions (supply voltage, load) is change in the stress on the voltage reference die. The Piezo junction effect explains that mechanical stress on band gap changes base to emitter voltage (VBE) of transistor and resistors which results in drift in the output voltage of the reference. Package, mold compound, PCB design and moisture in the environment are key contributing factors for this stress change.