4 Layout Consideration

TPS56x242/7 is SOT-563 package which is 1.60 mm × 1.60 mm and TPS56x201/8 is SOT-236 package which is 1.60 mm × 2.90 mm. The body size of TPS56x201/8 is bigger than TPS56x242/7. When doing co-layout, the relative positions between SOT-236 device and SOT-563 devices needs to be considered and comply with manufacturer's rules. There are two types of co-layout design. Figure 4-1 shows the mirror symmetrical co-layout design. This type of design needs to put one part on the front and another on the back of the board. The pin-out can match well with each other and follow with layout guidelines. Vias are required for VIN, SW and GND pin according to the load current. Figure 5-15 shows the piggyback co-layout design. This type of design can put both parts on same side of the board. Please make sure that the input capacitors of both devices are placed as close to the VIN pin to minimize trace impedance.

The recommend type 1 and type 2 co-layout design are shown in Figure 4-3 and Figure 4-4. For type 2, the input capacitor is placed as close as possible to VIN pin. Voltage feedback loop is placed away from the high-voltage switching trace and has ground shield. The trace of the FB node is as small as possible to avoid noise coupling. When soldered with TPS565201, the switching trace is short and wide enough. When soldered with TPS565242, the switching trace goes through from the top layer to the bottom layer then back to the top layer with the connecting inductor. Please keep in mind that do not allow switching current to flow under the device.