SBAA534 March 2022 ADC128S102-SEP , ADC128S102QML-SP , ADS1278-SP , ADS1282-SP , LF411QML-SP , LM101AQML-SP , LM111QML-SP , LM119QML-SP , LM124-SP , LM124AQML-SP , LM136A-2.5QML-SP , LM139-SP , LM139AQML-SP , LM148JAN-SP , LM158QML-SP , LM185-1.2QML-SP , LM185-2.5QML-SP , LM193QML-SP , LM4050QML-SP , LM6172QML-SP , LM7171QML-SP , LMH5401-SP , LMH5485-SEP , LMH5485-SP , LMH6628QML-SP , LMH6702QML-SP , LMH6715QML-SP , LMP2012QML-SP , LMP7704-SP , OPA4277-SP , OPA4H014-SEP , OPA4H199-SEP , THS4304-SP , THS4511-SP , THS4513-SP , TL1431-DIE , TL1431-SP , TLC2201-SP , TLV1704-SEP , TLV4H290-SEP , TLV4H390-SEP
The following chapters use an example design described by Table 1-1.
Parameter | Design Goal |
---|---|
Channel Count | 8 |
Bandwidth and Sampling Rate | 40 kHz, > 100 ksps |
Input Full Scale Range (FSR) | ±10-V FSR |
Common-Mode Voltage |
About 0 V common mode |
Target Resolution, ENOB |
> 16 bit |
Input Impedance (ZIN) Target |
> 100 kΩ |
Radiation hardness |
TID: > 50 krad, SEL: > 60 (MeV × cm2/mg) |
The TI Space Products Guide, Space-Grade Data Converters section shows that the ADS1278-SP best fits these requirements.
The next step is to identify the right ADC driver. For best noise immunity and linearity a fully differential amplifier (FDA) is preferred.
To identify the right product, the minimum unity gain bandwidth of such FDA must be understood. The ANALOG-ENGINEER’S CALCULATOR provides great assistance here.
Figure 1-2 illustrates that the Data Converters menu offers the Drive Wideband Delta-Sigma ADC item. The reference schematic in the figure shows all relevant component values. The white fields must be entered by the user, the gray fields are the resulting values. The very first variable to define is the minimum unity gain bandwidth (UGBW). In other words, up to what frequency must the gain of the amplifier be equal or greater than one. Since the ADC will cut off any information above the Nyquist or sample frequency divided by two, it is sufficient if the UGBW of the amplifier is about two-thirds of the sampling frequency. For example, for a sample rate of 1 kHz, look at a minimum UGBW of 636.6 Hz.
The selected ADC in the example of this report is a sigma-delta ADC. It is important to remember that a sigma-delta ADC is a one-bit ADC at the provided modulation frequency. The actual sample rate is only the frequency the full sample words come out of it. The relevant frequency for the AFE design is the modulation frequency which is much higher.
Due to the flexibility and complexity of modern ADCs it is not always straightforward to read the modulation frequency from the data sheet. The ADS1278-SP provides different operating modes that allow for different master clock rates. Figure 1-3 shows the actual modulation frequency is just one-fourth of the master clock. In the example, the ADS1278-SP operates in High-Speed mode: 128 ksps, fCLK is 32.786 MHz. FCLK divided by four results in 8.192 MHz for the actual modulation frequency.
Figure 1-5 illustrates the TI space product guide showing four FDAs. All four provide more than sufficient UGBW. As an example for this report, the lowest one (LMH5485-SP) with 850-MHz UGBW is selected.
With that selection it is now possible to fill the rest of the white fields in the ANALOG-ENGINEER’S CALCULATOR, see Figure 1-6.
Parameter | Description |
---|---|
Ro-dif | Ro-dif is the
“open-loop output impedance”. The LMH5485-SP Radiation
Hardened Assured (RHA) Negative Rail Input, Rail-to-Rail
Output, Precision, 850 MHz Fully Differential
Amplifier data sheet provides only the closed-loop
output impedance = 0.1 Ω. The Small-Signal Frequency Response vs Gain graph in the Typical Characteristics: 5 V Single Supply section of the LMH5485-SP data sheet provides the gain versus frequency curve. For the modulation frequency of 8.192 MHz, the graph shows about 38 dB, that is, about 80. With the relation of Ro-dif calculates as follows: 90 × 0.1 Ω = 8 Ω. |
Riso | Riso is typically tuned to a small value. Here "0" (0 Ω) is used. |
Rg and Rf | Rg and Rf must be the same for unity gain. "1k" (1 kΩ) is typically a good starting point. |
IPP | The LMH5485-SP data sheet allows for up to 75 mA of output current. An unnecessarily high output current would cause power loss and heating of the FDA which may cause a drift from the optimal working point. A value of "8m" (8 mA) is enough to make calculations in this example. |
fin | The required bandwidth is 40 kHz. With some margin, "50k" (50 kHz) is a good selection here. |
UGBW | The UGBW of FDA is "859M" (850 MHz). |
CSH | Use CSH from the Equivalent Analog Input Circuitry image in the ADS1278-SP Radiation Hardened 8-Ch Simultaneous-Sampling 24-Bit Analog-to-Digital Converter data sheet: "9p" (9 pF). |
CFILT | Prior defining leaves CFILT as the last entries - press the Calculate button to obtain the updated values for Cfilt_min "180p" (180 pF) and Cfilt_max "5.1n" (5.1 nF). Use "2.2n" (2.2 nF) as the value somewhat in between 5 nF and 180 pF. |
In this chapter the best fitting ADC and ADC-driver was selected with the help of the TI Space Products Guide and the ANALOG-ENGINEER’S CALCULATOR was used to determine its supporting circuitry, including all component values. Further, a basic understanding of the circuit and the role of each of the active and passive components was developed.
This chapter shows how to verify the example design towards the desired design goals with the help of both the TINA TI Simulator tool and the ANALOG-ENGINEER’S CALCULATOR. The section also shows how to verify that the signal chain performs to the full differential and common-mode input range of the ADC. Then the total noise performance and the linearity are observed to determine if the ENOB target can be met, followed by a stability analysis and verification of the input impedance. Finally, the chapter provides proof that the circuit meets the settling time requirement of the sample and hold capacitor of the ADC.
As Figure 2-1 shows, before the verification analysis can start, the design must first complete the attenuation and input buffer stage. The important design goals to remember here are a single-ended ±10-V input signal is translated into a ± 2.5-V differential signal for the ADC input and the input impedance must be > 100 kΩ.
For the input buffer, the LMP7704-SP device was selected. The resistor divider network of the attenuation stage brings the signal level down by a factor of four. The input signal generator VG1 is set to 240-kHz sine wave with ±10-V amplitude.
Figure 2-2 shows the selection of Transient… in the Analysis menu of TINA-TI and setting the simulation window from "0" to "100u" (100 μs).
The returned waveform in Figure 2-3 shows that the single-ended input signal with an amplitude of 10 V results into a differential output signal with an amplitude of 2.5 V. This amplitude takes advantage of the full input voltage range of the ADC for the best possible resolution.
To accomplish 16 ENOBs it is fundamental that the signal is significantly stronger than the noise floor of the AFE system. In other words, the SNR value must be high enough.
The ANALOG-ENGINEER’S CALCULATOR provides an easy way to determine the total SNR of the AFE system. Using the ANALOG-ENGINEER’S CALCULATOR, Figure 2-4 illustrates the selection of ADC + Signal Chain Noise from the Data Converters menu.
The Full Range Scale is 5 V and the ADC SNR value is read from the ADS1278-SP Radiation Hardened 8-Ch Simultaneous-Sampling 24-Bit Analog-to-Digital Converter data sheet. The value for the Signal Chain Noise at the converter input requires a bit more effort. Use the TINA-TI simulator to analyze the schematic from Figure 2-1 for its total noise, reference Figure 2-5 and Figure 2-6.
At 50 kHz - the highest frequency of interest with margin – TINA-TI returns 8.69 μV which can be entered into the ANALOG-ENGINEER’S CALCULATOR as shown in Figure 2-4.
The noise level for the voltage reference can be identified in a similar way with TINA-TI or simply read from the data sheet if just a regular shunt voltage reference device is used. For demonstration purposes, "2.21u" (2.21 μV) is chosen. After selecting the OK button, the tool returns 102.94 dB for the combined SNR.
Applying the standard conversion formula ENOB = (SNR – 1.76) / 6.02 dB, this calculates to ENOB = 16.81 bits.
The Harmonic Distortion Over Frequency graph, Figure 2-7, from the LMH5485-SP data sheet shows distortion of –118 dBc for 50 kHz and below. Its absolute value of 118 dB is significantly enough higher than the previously-identified combined SNR of 102.94 dB. Distortion from non-linearity can therefore be ignored.
This section looks at the frequency response of the input circuit to verify that the bandwidth is wide enough to preserve the signal of interest across its entire bandwidth but also be narrow enough to act as an anti-aliasing filter.
For this, the signal chain from signal input to ADC input must be analyzed, in other words, the same circuit as shown in Figure 2-1. Figure 2-8 shows the selection of the AC Transfer Characteristic option in the Analysis menu in the TINA-TI simulator. Use this option to analyze the frequency response for amplitude and phase.
For the lower frequencies, the gain is stable at –12.04 dB. The –3-dB bandwidth (–15.04 dB) shows at 542.96 kHz, see Figure 2-9. This is very well above the cutoff frequency of 60 kHz of the digital filter response of the ADS1278. The linearity requirement for the bandwidth of interest is clearly met.
The second concern is on aliasing. ADS1278-SP is a sigma-delta modulator. In this example, the device modulates the signal with 8.192 MHz. Accordingly, Nyquist is at fmod / 2 = 4.096 MHz. The gain shows –57 dB at that frequency which means only 45-dB suppression at the Nyquist frequency. The result from simulation is an indication that further measures for suppression of frequencies at and above 4 MHz might be required.