SPRAAR7J November   2018  – February 2023 66AK2G12 , AM1806 , AM1808 , AM2431 , AM2432 , AM2434 , AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3358-EP , AM3359 , AM3871 , AM3874 , AM3892 , AM3894 , AM4376 , AM4377 , AM4378 , AM4379 , AM5706 , AM5708 , AM5716 , AM5718 , AM5726 , AM5728 , AM5729 , AM5746 , AM5748 , AM5749 , AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442 , AM6526 , AM6528 , AM6546 , AM6548 , BQ24392-Q1 , HD3SS6126 , LP8727 , OMAP-L137 , OMAP5912 , TMS320C6745 , TMS320DM335 , TMS320DM355 , TMS320DM365 , TMS320DM368 , TMS320DM369 , TMS320DM6441 , TMS320DM6443 , TMS320DM6446 , TMS320DM6467 , TMS320DM8127 , TMS320DM8147 , TMS320DM8148 , TMS320DM8165 , TMS320DM8167 , TMS320DM8168 , TMS320VC5506 , TMS320VC5507 , TMS320VC5509A , TS3USB221A-Q1 , TS3USBA225 , TSU5511 , TSU5611 , TSU6111 , TSU6111A , TSU6721 , TSU8111

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Scope
    2. 1.2 Critical Signals
  4. 2General High-Speed Signal Routing
    1. 2.1 PCB Fiber Weave Mitigation
    2. 2.2 High-Speed Signal Trace Lengths
    3. 2.3 High-Speed Signal Trace Length Matching
    4. 2.4 High-Speed Signal Reference Planes
  5. 3High-Speed Differential Signal Routing
    1. 3.1  Differential Signal Spacing
    2. 3.2  High-Speed Differential Signal Rules
    3. 3.3  Symmetry in the Differential Pairs
    4. 3.4  Crosstalk Between the Differential Signal Pairs
    5. 3.5  Connectors and Receptacles
    6. 3.6  Via Discontinuity Mitigation
    7. 3.7  Back-Drill Stubs
    8. 3.8  Increase Via Anti-Pad Diameter
    9. 3.9  Equalize Via Count
    10. 3.10 Surface-Mount Device Pad Discontinuity Mitigation
    11. 3.11 Signal Bending
    12. 3.12 Suggested PCB Stackups
    13. 3.13 ESD/EMI Considerations
    14. 3.14 ESD/EMI Layout Rules
  6. 4References
  7.   A Device Layout Parameters
  8.   Revision History

1.2 Critical Signals

A primary concern when designing a system is accommodating and isolating high-speed signals. As high-speed signals are most likely to impact or be impacted by other signals, they must be laid out early (preferably first) in the PCB design process to ensure that prescribed routing rules can be followed.

#GUID-67EBD705-3FD9-478D-B022-90C9907D5F4C/TABLE_EVM_53M_CTB outlines the high-speed interface signals requiring the most attention when laying out a PCB that incorporates a Texas Instruments™ System-on-Chip (SoC).

Table 1-1 Critical Signals
Signal Name Description
DP Universal Serial Bus (USB) 2.0 differential data pair, positive
DM Universal Serial Bus (USB) 2.0 differential data pair, negative
SSTXP SuperSpeed Universal Serial Bus (SSUSB) differential data pair, TX, positive
SSTXN SuperSpeed Universal Serial Bus (SSUSB) differential data pair, TX, negative
SSRXP SuperSpeed Universal Serial Bus (SSUSB) differential data pair, RX, positive
SSRXN SuperSpeed Universal Serial Bus (SSUSB) differential data pair, RX, negative
SATA_RXP Serial ATA (SATA) differential data pair, RX, positive
SATA_RXN Serial ATA (SATA) differential data pair, RX, negative
SATA_TXP Serial ATA (SATA) differential data pair, TX, positive
SATA_TXN Serial ATA (SATA) differential data pair, TX, negative
PCIe_RXP PCI-Express (PCIe) differential data pair, RX,positive
PCIE_RXN PCI-Express (PCIe) differential data pair, RX,negative
PCIE_TXP PCI-Express (PCIe) differential data pair, TX,positive
PCIE_TXN PCI-Express (PCIe) differential data pair, TX,negative
HDMI_CLOCKx High-Definition Multimedia Interface (HDMI) differential clock pair, positive or negative
HDMI_CLOCKy High-Definition Multimedia Interface (HDMI) differential clock pair, positive or negative
HDMI_DATA2x High-Definition Multimedia Interface (HDMI) differential data pair, positive or negative
HDMI_DATA2y High-Definition Multimedia Interface (HDMI) differential data pair, positive or negative
HDMI_DATA1x High-Definition Multimedia Interface (HDMI) differential data pair, positive or negative
HDMI_DATA1y High-Definition Multimedia Interface (HDMI) differential data pair, positive or negative
HDMI_DATA0x High-Definition Multimedia Interface (HDMI) differential data pair, positive or negative
HDMI_DATA0y High-Definition Multimedia Interface (HDMI) differential data pair, positive or negative
SGMII_TXP Serial Gigabit Media Independant Interface (SGMII) differential data pair, TX, positive
SGMII_TXN Serial Gigabit Media Independant Interface (SGMII) differential data pair, TX, negative
SGMII_RXP Serial Gigabit Media Independant Interface (SGMII) differential data pair, RX, positive
SGMII_RXN Serial-Gigabit Media Independant Interface (SGMII) differential data pair, RX, negative
CSI_RXCLKN CSI Differential Receive Clock Input (negative)
CSI_RXCLKP CSI Differential Receive Clock Input (positive)
CSI_RXN0 CSI Differential Receive Input (negative)
CSI_RXN1 CSI Differential Receive Input (negative)
CSI_RXN2 CSI Differential Receive Input (negative)
CSI_RXN3 CSI Differential Receive Input (negative)
CSI_RXP0 CSI Differential Receive Input (positive)
CSI_RXP1 CSI Differential Receive Input (positive)
CSI_RXP2 CSI Differential Receive Input (positive)
CSI_RXP3 CSI Differential Receive Input (positive)