SPRAAR7J November   2018  – February 2023 66AK2G12 , AM1806 , AM1808 , AM2431 , AM2432 , AM2434 , AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3358-EP , AM3359 , AM3871 , AM3874 , AM3892 , AM3894 , AM4376 , AM4377 , AM4378 , AM4379 , AM5706 , AM5708 , AM5716 , AM5718 , AM5726 , AM5728 , AM5729 , AM5746 , AM5748 , AM5749 , AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442 , AM6526 , AM6528 , AM6546 , AM6548 , BQ24392-Q1 , HD3SS6126 , LP8727 , OMAP-L137 , OMAP5912 , TMS320C6745 , TMS320DM335 , TMS320DM355 , TMS320DM365 , TMS320DM368 , TMS320DM369 , TMS320DM6441 , TMS320DM6443 , TMS320DM6446 , TMS320DM6467 , TMS320DM8127 , TMS320DM8147 , TMS320DM8148 , TMS320DM8165 , TMS320DM8167 , TMS320DM8168 , TMS320VC5506 , TMS320VC5507 , TMS320VC5509A , TS3USB221A-Q1 , TS3USBA225 , TSU5511 , TSU5611 , TSU6111 , TSU6111A , TSU6721 , TSU8111

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Scope
    2. 1.2 Critical Signals
  4. 2General High-Speed Signal Routing
    1. 2.1 PCB Fiber Weave Mitigation
    2. 2.2 High-Speed Signal Trace Lengths
    3. 2.3 High-Speed Signal Trace Length Matching
    4. 2.4 High-Speed Signal Reference Planes
  5. 3High-Speed Differential Signal Routing
    1. 3.1  Differential Signal Spacing
    2. 3.2  High-Speed Differential Signal Rules
    3. 3.3  Symmetry in the Differential Pairs
    4. 3.4  Crosstalk Between the Differential Signal Pairs
    5. 3.5  Connectors and Receptacles
    6. 3.6  Via Discontinuity Mitigation
    7. 3.7  Back-Drill Stubs
    8. 3.8  Increase Via Anti-Pad Diameter
    9. 3.9  Equalize Via Count
    10. 3.10 Surface-Mount Device Pad Discontinuity Mitigation
    11. 3.11 Signal Bending
    12. 3.12 Suggested PCB Stackups
    13. 3.13 ESD/EMI Considerations
    14. 3.14 ESD/EMI Layout Rules
  6. 4References
  7.   A Device Layout Parameters
  8.   Revision History

A Device Layout Parameters

Table A-1 AM335x/AM437x/AMIC1xx
Parameter MIN TYP MAX Unit
USB2.0 Tracelength (total) 4000 12000 Mils
Skew within any USB2.0 differential pair 50 Mils
USB2.0 DP/DM pair differential impedance 81 90 99 Ω
USB2.0 DP/DM pair common-mode impedance 40.5 45 49.5 Ω
Number of stubs allowed on any USB differential pair trace (total) 0 Stubs
Number of vias allowed on each USB2.0 differential trace (total) 4 Vias
Number of test points permitted on any USB differential pair trace (total) 0 Test Points
USB differential pair to clock or high-speed periodic signal trace spacing 50 Mils
USB differential pair to any other signal trace spacing 30 Mils
Table A-2 AM57xx/DRA7xx
Parameter MIN TYP MAX Unit
USB3.0 (SuperSpeed) Tracelength (Total) 3500 Mils
Serial-ATA (SATA) Tracelength (Total) 3500 Mils
PCI-Express (PCIe) Tracelength (Total) 4700 Mils
SuperSpeed Insertion Loss at 2.5GHz (device to connector) Refer to USB Specification dB
USB2.0 Tracelength (Total) 4000 12000 Mils
HDMI Tracelength (Total) 4000 Mils
Skew within any USB3/SATA/PCIe/HDMI differential pair 5 Mils
Skew between all PCIe RX pairs (Total) 550 Mils
Skew between all PCIe TX pairs (Total) 550 Mils
Skew within any USB2.0 differential pair 50 Mils
USB2.0 DP or DM pair differential impedance 81 90 99 Ω
USB2.0 DP or DM pair single-ended impedance 40.5 45 49.5 Ω
SuperSpeed SSRX or SSTX pair differential impedance 83.7 90 96.3 Ω
PCI-Express RX or TX pair differential impedance 90 100 110 Ω
PCI-Express RX or TX trace single-ended impedance 51 60 69 Ω
Serial-ATA RX or TX pair differential impedance 85 100 115 Ω
HDMI TMDS differential impedance 90 100 110 Ω
Number of stubs allowed on any differential pair trace (Total) 0 Stubs
Number of vias allowed on any USB3 differential trace (Total) 2 Vias
Number of vias allowed on any PCIe/SATA differential trace (Total) 0 Vias
Number of vias allowed on each USB2.0 differential trace (Total) 4 Vias
Number of vias allowed on each TMDS differential trace (HDMI)(Total) 0 Vias
Number of test points permitted on any differential pair trace (Total) 0 Test Points
Differential pair to clock or high-speed periodic signal trace spacing 50 Mils
Differential pair to any other signal trace spacing 30 Mils
Table A-3 KeyStone II - K2K, K2H, K2L, and K2E Devices
Parameter MIN TYP MAX Unit
USB3.0 (SuperSpeed) Tracelength (Total) 5500 Mils
Serial-ATA (SATA) Tracelength (Total) 5500 Mils
PCI-Express (PCle) Tracelength (Total) 5500 Mils
SuperSpeed Insertion Loss at 2.5 GHz (device to connector) Refer to USB Specification dB
USB2.0 Tracelength (Total) 4000 12000 Mils
Skew within any USB3/SATA/PCIe differential pair 5 Mils
Skew between all PCIe RX pairs (Total) 550 Mils
Skew between all PCIe TX pairs (Total) 550 Mils
Skew within any USB2.0 differential pair 50 Mils
USB2.0 DP or DM pair differential impedance 81 90 99 Ω
USB2.0 DP or DM pair common mode impedance 40.5 45 49.5 Ω
SuperSpeed SSRX or SSTX pair differential impedance 83.7 90 96.3 Ω
PCI-Express RX or TX pair differential impedance 90 100 110 Ω
PCI-Express RX or TX trace single-ended impedance 51 60 69 Ω
Serial-ATA RX or TX pair differential impedance 85 100 115 Ω
Number of stubs allowed on any differential pair trace (Total) 0 Stubs
Number of vias allowed on USB3 differential trace (Total) 2 Vias
Number of vias allowed on any PCIe/SATA differential trace (Total) 0 Vias
Number of vias allowed on each USB2.0 differential trace (Total) 4 Vias
Number of test points permitted on any differential pair trace (Total) 0 Test Points
Differential pair to clock or high-speed periodic signal trace spacing 50 Mils
Differential pair to any other signal trace spacing 30 Mils
Table A-4 KeyStone II - K2G (66AK2G0x/66AK2G1x) Devices
Parameter MIN TYP MAX Unit
PCI-Express (PCIe) Tracelength (Total) 5500 Mils
USB2.0 Tracelength (Total) 4000 12000 Mils
Skew within any PCIe differential pair 5 Mils
Skew between all PCIe RX pairs (Total) 550 Mils
Skew between all PCIe TX pairs (Total) 550 Mils
Skew within any USB2.0 differential pair 50 Mils
USB2.0 DP or DM pair differential impedance 81 90 99 Ω
USB2.0 DP or DM pair single-ended impedance 40.5 45 49.5 Ω
PCI-Express RX or TX pair differential impedance 90 100 110 Ω
PCI-Express RX or TX trace single-ended impedance 51 60 69 Ω
Number of stubs allowed on any differential pair trace (Total) 0 Stubs
Number of vias allowed on any PCIe differential trace (Total) 0 Vias
Number of vias allowed on each USB2.0 differential trace (Total) 4 Vias
Number of test points permitted on any differential pair trace (Total) 0 Test Points
Differential pair to clock or high-speed periodic signal trace spacing 50 Mils
Differential pair to any other signal trace spacing 30 Mils
Table A-5 AM65xx/DRA80xM
Parameter MIN TYP MAX Unit
USB3.1 GEN1 Tracelength (Total) 4000 Mils
PCI-Express (PCIe) Tracelength (Total) 4000 Mils
Serial Gigabit Media Independent Interface (SGMII) Tracelength (Total) 7500 Mils
USB2.0 Tracelength (Total) 4000 12000 Mils
SuperSpeed Insertion Loss at 2.5GHz (device to connector) Refer to USB Specification dB
Skew within any USB3/PCIe/SGMII differential pair 5 Mils
Skew between all PCIe RX pairs (Total) 6 ns
Skew between all PCIe TX pairs (Total) 1.5 ns
Skew within any USB2.0 differential pair 50 Mils
USB2.0 DP or DM pair differential impedance 81 90 99 Ω
SuperSpeed SSRX or SSTX pair differential impedance 90.25 95 99.75 Ω
PCI-Express RX or TX pair differential impedance 90.25 95 99.75 Ω
SGMII RX/TX/RXCLK/TXCLK pair differential impedance 90.25 95 99.75 Ω
Number of stubs allowed on any differential pair trace (Total) 0 Stubs
Number of vias allowed on any USB3/PCIe/SGMII differential trace (Total) 2 Vias
Number of vias allowed on each USB2.0 differential trace (Total) 4 Vias
Number of test points permitted on any differential pair trace (Total) 0 Test Points
Differential pair to clock or high-speed periodic signal trace spacing 50 Mils
Differential pair to any other signal trace spacing 30 Mils
Table A-6 AM64x
Parameter MIN TYP MAX Unit
USB3.1 GEN1 Tracelength (Total) 5500 Mils
PCI-Express (PCIe) Tracelength (Total) 5500 Mils
USB2.0 Tracelength (Total) 4000 12000 Mils
SuperSpeed Insertion Loss at 2.5GHz (device to connector) Refer to USB Specification dB
Skew within any USB3/PCIe differential pair 5 Mils
Skew between all PCIe RX pairs (Total) 6 ns
Skew between all PCIe TX pairs (Total) 1.5 ns
Skew within any USB2.0 differential pair 50 Mils
USB2.0 DP or DM pair differential impedance 81 90 99 Ohms
SuperSpeed SSRX or SSTX pair differential impedance 90.25 95 99.75 Ohms
PCI-Express RX or TX pair differential impedance 90.25 95 99.75 Ohms
Number of stubs allowed on any differential pair trace (Total) 0 Stubs
Number of vias allowed on any USB3/PCIe differential trace (Total) 2 Vias
Number of vias allowed on each USB2.0 differential trace (Total) 4 Vias
Number of test points permitted on any differential pair trace (Total) 0 Test Points
Differential pair to clock or high-speed periodic signal trace spacing 50 Mils
Differential pair to any other signal trace spacing 30 Mils
Table A-7 AM62x (Preliminary Data)
Parameter MIN TYP MAX Unit
USB2.0 Tracelength (Total) 4000 12000 Mils
Skew within any USB2.0 differential pair 50 Mils
USB2.0 DP or DM pair differential impedance 81 90 99 Ohms
CSI Tracelength (Total) 10 Inches
CSI differential pair skew Must satisfy mode-conversion S-parameters (1)
CSI pair differential impedance 85 100 115 Ohms (2)
CSI single-ended impedance 50 Ohms
CSI lane skew 40 ps (3)
Number of stubs allowed on any differential pair trace (Total) 0 Stubs
Number of vias allowed on each USB2.0 differential trace (Total) 4 Vias
Number of vias allowed on each CSI differential trace (Total) 2 Vias
Number of test points permitted on any differential pair trace (Total) 0 Test Points
Differential pair to clock or high-speed periodic signal trace spacing 50 Mils
Differential pair to any other signal trace spacing 30 Mils
  1. Defined in MIPI D-PHY spec; includes sdc12, scd21, scd12, sdc21, scd11, sdc11, scd22, and sdc22. General estimate is UI/50 (where UI = 400 ps for 1.25 GHz).
  2. Because the MIPI signals are used for low-power, single-ended signaling in addition to their high-speed differential implementation, the pairs must be loosely coupled.
  3. Defined by MIPI spec as 0.1 x UI (where UI = 400 ps for 1.25 GHz).
Table A-8 AM62Ax (Preliminary Data)
Parameter MIN TYP MAX Unit
USB2.0 Tracelength (Total) 4000 12000 Mils
Skew within any USB2.0 differential pair 50 Mils
USB2.0 DP or DM pair differential impedance 81 90 99 Ohms
CSI Tracelength (Total) 10 Inches
CSI differential pair skew Must satisfy mode-conversion S-parameters (1)
CSI pair differential impedance 85 100 115 Ohms (2)
CSI single-ended impedance 50 Ohms
CSI lane skew 40 ps (3)
Number of stubs allowed on any differential pair trace (Total) 0 Stubs
Number of vias allowed on each USB2.0 differential trace (Total) 4 Vias
Number of vias allowed on each CSI differential trace (Total) 2 Vias
Number of test points permitted on any differential pair trace (Total) 0 Test Points
Differential pair to clock or high-speed periodic signal trace spacing 50 Mils
Differential pair to any other signal trace spacing 30 Mils
  1. Defined in MIPI D-PHY spec; includes sdc12, scd21, scd12, sdc21, scd11, sdc11, scd22, and sdc22. General estimate is UI/50 (where UI = 400 ps for 1.25 GHz).
  2. Because the MIPI signals are used for low-power, single-ended signaling in addition to their high-speed differential implementation, the pairs must be loosely coupled.
  3. Defined by MIPI spec as 0.1 x UI (where UI = 400 ps for 1.25 GHz).