Gehäuseinformationen
| Gehäuse | Pins BGA (ZFF) | 419 |
| Betriebstemperaturbereich (°C) 0 to 55 |
| Gehäusemenge | Träger 60 | JEDEC TRAY (5+1) |
Merkmale von DLPC6401
- Provides a 30-Bit Input Pixel Interface:
- YUV, YCrCb, or RGB Data Format
- 8, 9, or 10 Bits per Color
- Pixel Clock Support up to 150 MHz
- Provides a Single Channel, LVDS Based,
Flat-Panel Display (FPD)-Link Compatible Input Interface:- Supports Sources up to a 90-MHz Effective Pixel Clock Rate
- Four Demodulated Pixel-Mapped Modes Supported for 8, 9, 10 YUV, YCrCb, or RGB Formatted Inputs
- Supports 45- to 120-Hz Frame Rates
- Full Support for Diamond 0.45 WXGA
- High-Speed, Double Data Rate (DDR) Digital Micromirror Device (DMD) Interface
- 149.33-MHz ARM926™ Microprocessor
- Microprocessor Peripherals:
- Programmable Pulse-Width Modulation (PWM) and Capture Timers
- Two I2C Ports
- Two UART Ports (for Debug Only)
- 32 KB of Internal RAM
- Dedicated LED PWM Generators
- Image Processing:
- Auto-Lock for Standard, Wide, and Black Border
- 1D Keystone Correction
- Programmable Degamma
- On-Screen Display (OSD)
- Splash Screen Display Support
- Integrated Clock Generation Circuitry
- Operates on a Single 32-MHz Crystal
- Integrated Spread Spectrum Clocking
- Integrated 64-Mb Frame Memory Eliminates the Need for External High-Speed Memory
- External Memory Support: Parallel Flash for Microprocessor and PWM Sequence
- System Control:
- DMD Power and Reset Driver Control
- DMD Horizontal and Vertical Image Flip
- JTAG Boundary Scan Test Support
- 419-Pin Plastic Ball Grid Array Package
Beschreibung von DLPC6401
The DLPC6401 digital controller, part of the DLP4500 (.45 WXGA) chipset, supports reliable operation of the DLP4500 digital micromirror device (DMD). The DLPC6401 controller provides a convenient, multi-functional interface between system electronics and the DMD, enabling small form factor and high resolution HD displays.