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DRA74P

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Multicore-SoC-Prozessoren mit ISP und pinkompatibel mit SoC-Prozessoren DRA74x

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DRA74P

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Produktdetails

Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1500 Coprocessors 2 Dual Arm Cortex-M4 CPU 32-bit Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100/1000, 2-Port 1Gb switch PCIe 1 PCIe Gen 2 Hardware accelerators 1 Image Subsystem Processor, 1 Image Video Accelerator, 2 Viterbi Decoder, Audio Tracking Features Multimedia Operating system Android, Linux, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125
Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1500 Coprocessors 2 Dual Arm Cortex-M4 CPU 32-bit Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100/1000, 2-Port 1Gb switch PCIe 1 PCIe Gen 2 Hardware accelerators 1 Image Subsystem Processor, 1 Image Video Accelerator, 2 Viterbi Decoder, Audio Tracking Features Multimedia Operating system Android, Linux, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125
FCCSP (ABZ) 760 529 mm² 23 x 23
  • Architecture Designed for Infotainment Applications
  • Video, Image, and Graphics Processing Support
    • Full-HD Video (1920 × 1080p, 60 fps)
    • Multiple Video Input and Video Output
    • 2D and 3D Graphics
  • Dual Arm® Cortex®-A15 Microprocessor Subsystem
  • Up to Two C66x Floating-Point VLIW DSP
    • Fully Object-Code Compatible with C67x and C64x+
    • Up to Thirty-Two 16 x 16-Bit Fixed-Point Multiplies per Cycle
  • Up to 2.5MB of On-Chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) Interconnects
  • Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
    • Supports up to DDR2-800 and DDR3-1333
    • Up to 2GB Supported per EMIF
  • Dual ARM® Cortex®-M4 Image Processing Units (IPU)
  • Up to Two Embedded Vision Engines (EVEs)
  • Imaging Subsystem (ISS)
    • Image Signal Processor (ISP)
    • Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
    • One Camera Adaptation Layer (CAL_B)
  • IVA Subsystem
  • Display Subsystem
    • Display Controller with DMA Engine and up to Three Pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • Video Processing Engine (VPE)
  • 2D-Graphics Accelerator (BB2D) Subsystem
    • Vivante® GC320 Core
  • Dual-Core PowerVR® SGX544 3D GPU
  • Two Video Input Port (VIP) Modules
    • Support for up to Eight Multiplexed Input Ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) Controller
  • 2-Port Gigabit Ethernet (GMAC)
  • Sixteen 32-Bit General-Purpose Timers
  • 32-Bit MPU Watchdog Timer
  • Five Inter-Integrated Circuit (I2C) Ports
  • HDQ™/1-Wire® Interface
  • SATA Interface
  • Media Local Bus (MLB) Subsystem
  • Ten Configurable UART/IrDA/CIR Modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) Modules
  • SuperSpeed USB 3.0 Dual-Role Device
  • Three High-Speed USB 2.0 Dual-Role Devices
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 Subsystems with Two 5-Gbps Lanes
    • One 2-Lane Gen2-Compliant Port
    • or Two 1-Lane Gen2-Compliant Ports
  • Up to Two Controller Area Network (DCAN) Modules
    • CAN 2.0B Protocol
  • Modular Controller Area Network (MCAN) Module
    • CAN 2.0B Protocol with Available FD (Flexible Data Rate) Functionality
  • Up to 247 General-Purpose I/O (GPIO) Pins
  • Real-Time Clock Subsystem (RTCSS)
  • Device Security Features
    • Hardware Crypto Accelerators and DMA
    • Firewalls
    • JTAG® Lock
    • Secure Keys
    • Secure ROM and Boot
    • Customer Programmable Keys and OTP Data
  • Power, Reset, and Clock Management
  • On-Chip Debug with CTools Technology
  • 28-nm CMOS Technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABZ)
  • Architecture Designed for Infotainment Applications
  • Video, Image, and Graphics Processing Support
    • Full-HD Video (1920 × 1080p, 60 fps)
    • Multiple Video Input and Video Output
    • 2D and 3D Graphics
  • Dual Arm® Cortex®-A15 Microprocessor Subsystem
  • Up to Two C66x Floating-Point VLIW DSP
    • Fully Object-Code Compatible with C67x and C64x+
    • Up to Thirty-Two 16 x 16-Bit Fixed-Point Multiplies per Cycle
  • Up to 2.5MB of On-Chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) Interconnects
  • Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
    • Supports up to DDR2-800 and DDR3-1333
    • Up to 2GB Supported per EMIF
  • Dual ARM® Cortex®-M4 Image Processing Units (IPU)
  • Up to Two Embedded Vision Engines (EVEs)
  • Imaging Subsystem (ISS)
    • Image Signal Processor (ISP)
    • Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
    • One Camera Adaptation Layer (CAL_B)
  • IVA Subsystem
  • Display Subsystem
    • Display Controller with DMA Engine and up to Three Pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • Video Processing Engine (VPE)
  • 2D-Graphics Accelerator (BB2D) Subsystem
    • Vivante® GC320 Core
  • Dual-Core PowerVR® SGX544 3D GPU
  • Two Video Input Port (VIP) Modules
    • Support for up to Eight Multiplexed Input Ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) Controller
  • 2-Port Gigabit Ethernet (GMAC)
  • Sixteen 32-Bit General-Purpose Timers
  • 32-Bit MPU Watchdog Timer
  • Five Inter-Integrated Circuit (I2C) Ports
  • HDQ™/1-Wire® Interface
  • SATA Interface
  • Media Local Bus (MLB) Subsystem
  • Ten Configurable UART/IrDA/CIR Modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) Modules
  • SuperSpeed USB 3.0 Dual-Role Device
  • Three High-Speed USB 2.0 Dual-Role Devices
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 Subsystems with Two 5-Gbps Lanes
    • One 2-Lane Gen2-Compliant Port
    • or Two 1-Lane Gen2-Compliant Ports
  • Up to Two Controller Area Network (DCAN) Modules
    • CAN 2.0B Protocol
  • Modular Controller Area Network (MCAN) Module
    • CAN 2.0B Protocol with Available FD (Flexible Data Rate) Functionality
  • Up to 247 General-Purpose I/O (GPIO) Pins
  • Real-Time Clock Subsystem (RTCSS)
  • Device Security Features
    • Hardware Crypto Accelerators and DMA
    • Firewalls
    • JTAG® Lock
    • Secure Keys
    • Secure ROM and Boot
    • Customer Programmable Keys and OTP Data
  • Power, Reset, and Clock Management
  • On-Chip Debug with CTools Technology
  • 28-nm CMOS Technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABZ)

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.
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Technische Dokumentation

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Typ Titel Datum
* Data sheet DRA75xP, DRA74xP Infotainment Applications Processor Silicon Revision 1.0 datasheet (Rev. F) PDF | HTML 10 Dez 2018
* Errata DRA7xx Silicon Errata (Rev. B) PDF | HTML 08 Sep 2024
* User guide DRA77xP, DRA76xP, DRA75xP, DRA74xP Technical Reference Manual (Rev. D) PDF | HTML 25 Mai 2024
Application note Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 05 Mai 2021
More literature Building your application with security in mind (Rev. E) 28 Okt 2020
Application note IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 24 Aug 2020
Application note AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 06 Jan 2020
Application note Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 11 Jun 2019
Application note Achieving Early CAN Response on DRA7xx Devices 28 Nov 2018
Application note DRA74x_75x/DRA72x Performance (Rev. A) 31 Okt 2018
Application note Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 14 Sep 2018
Application note The Implementation of YUV422 Output for SRV 02 Aug 2018
Application note MMC DLL Tuning (Rev. B) 31 Jul 2018
Application note Integrating AUTOSAR on TI SoC: Fundamentals 18 Jun 2018
Application note ECC/EDC on TDAxx (Rev. B) 13 Jun 2018
Application note Tools and Techniques to Root Case Failures in Video Capture Subsystem 12 Jun 2018
Application note Sharing VPE Between VISIONSDK and PSDKLA 04 Mai 2018
Application note Android Boot Optimization on DRA7xx Devices (Rev. A) 13 Feb 2018
Application note Flashing Utility - mflash 09 Jan 2018
Application note Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 30 Nov 2017
Application note Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 07 Nov 2017
Application note A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 03 Nov 2017
Application note Optimization of GPU-Based Surround View on TI’s TDA2x SoC 12 Sep 2017
Application note Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 14 Aug 2017
Application note Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 12 Jul 2017
White paper Revolutionize the automotive cockpit 02 Jun 2017
Application note Linux Boot Time Optimizations on DRA7xx Devices 31 Mär 2017
Application note Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 17 Feb 2017
Application note Early Splash Screen on DRA7x Devices 31 Jan 2017
Application note Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 15 Dez 2016
Application note Gstreamer Migration Guidelines 26 Apr 2016
User guide Jacinto6 Android Video Decoder Software Design Specification User's Guide 21 Apr 2016
User guide Jacinto6 Android Video Encoder Software Design Specification User's Guide 21 Apr 2016
Application note Flashing Binaries to DRA7xx Factory Boards Using DFU 14 Apr 2016
Application note Tools and Techniques for Audio Debugging 13 Apr 2016
Application note Debugging Tools and Techniques With IPC3.x 30 Mär 2016
Application note Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 15 Jan 2016
White paper Informational ADAS as Software Upgrade to Today’s Infotainment Systems 14 Okt 2014
Application note Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 13 Aug 2014
White paper Today’s high-end infotainment soon becoming mainstream 02 Jun 2014

Design und Entwicklung

Lösungen für die Stromversorgung

Verfügbare Lösungen für die Stromversorgung für den DRA74P finden. TI bietet Stromversorgungslösungen für Ein-Chip-Systeme (SoCs), Prozessoren, Mikrocontroller, Sensoren und feldprogrammierbare Gate-Arrays (FPGAs) von TI und von Fremdherstellern an.

Lösungen anzeigen
Evaluierungsplatine

J6PEVM577P — DRA7xP-Evaluierungsmodul

The DRA77xP/DRA76xP-ACD is an evaluation platform designed to allow scalability and re-use across DRA77xP and DRA76xP JacintoTM Infotainment System-on-Chips (SoCs), it is based on Jacinto DRA77xP SoC that incorporates a heterogeneous, scalable architecture that includes a mix of two ARM Cortex-A15 (...)

Von: SVTRONICS INC
Benutzerhandbuch: PDF
Partner-Website besuchen
Software-Entwicklungskit (SDK)

PROCESSOR-SDK-ANDROID-AUTOMOTIVE-DRA7X

Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

Produkte
ARM-basierte Prozessoren
DRA710 — 600 MHz-Arm Cortex-A15-SoC-Prozessor mit Grafik für Infotainment und Cluster DRA712 — SoC-Prozessor Arm Cortex-A15, 600 MHz, mit Grafik & Dual Arm Cortex M4 für Infotainment & Kombiinstr DRA714 — SoC-Prozessor Arm Cortex-A15, 600 MHz, mit Grafik & DSP für Infotainment & Kombiinstrument DRA716 — SoC-Prozessor Arm Cortex-A15, 800 MHz, mit Grafik & DSP für Infotainment & Kombiinstrument DRA718 — SoC-Prozessor Arm Cortex-A15, 1 GHz, mit Grafik & DSP für Infotainment & Kombiinstrument DRA722 — SoC-Prozessor, 800 MHz, Arm Cortex-A15 mit Grafik und DSP für Infotainment & Cluster in Fahrzeugen DRA724 — SoC-Prozessor, 1 GHz, Arm Cortex-A15 mit Grafik und DSP für Infotainment & Cluster in Fahrzeugen DRA725 — SoC-Prozessor, 1,2 GHz, Arm Cortex-A15 mit Grafik und DSP für Infotainment & Cluster in Fahrzeugen DRA726 — Arm Cortex-A15, 1,5 GHz, mit Grafik & DSP für Infotainment & Kombiinstrument DRA74P — Multicore-SoC-Prozessoren mit ISP und pinkompatibel mit SoC-Prozessoren DRA74x DRA75P — Multicore-SoC-Prozessoren mit ISP und pinkompatibel mit SoCs DRA75x für Infotainment-Anwendungen DRA76P — Hochleistungs-Multicore-SoC-Prozessoren mit ISP für digitale Cockpit-Anwendungen DRA77P — Hochleistungs-Multi-Core SoCs mit erweiterten Peripheriegeräten und ISP für digitale Cockpit-Anwendu DRA790 — SoC-Prozessor Arm Cortex-A15, 300 MHz, mit C66x-DSP, 500 MHz, für Audioverstärker DRA791 — SoC-Prozessor Arm Cortex-A15, 300 MHz, mit C66x-DSP, 750 MHz, für Audioverstärker DRA793 — SoC-Prozessor Arm Cortex-A15, 500 MHz, mit C66x-DSP, 750 MHz, für Audioverstärker DRA797 — SoC-Prozessor Arm Cortex-A15, 800 MHz, mit C66x-DSP, 750 MHz, für Audioverstärker
Digitale Signalprozessoren (DSPs)
DRA780 — SoC-Prozessor mit 500 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA781 — SoC-Prozessor mit 750 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA782 — SoC-Prozessor mit 2x 500 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA783 — SoC-Prozessor mit 2x 750 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA785 — SoC-Prozessor mit 2x 1000 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA786 — SoC-Prozessor mit 2x 500 MHz C66x DSP und 2 Dual-Arm Cortex-M4 & EVE für Audioverstärker DRA787 — SoC-Prozessor mit 2x 750 MHz C66x DSP und 2 Dual-Arm Cortex-M4 & EVE für Audioverstärker DRA788 — SoC-Prozessor mit 2x 1000 MHz C66x DSP und 1x EVE und 2 Dual Arm Cortex-M4 für Audioverstärker
Download-Optionen
Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X — PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X

Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

Produkte
ARM-basierte Prozessoren
DRA710 — 600 MHz-Arm Cortex-A15-SoC-Prozessor mit Grafik für Infotainment und Cluster DRA712 — SoC-Prozessor Arm Cortex-A15, 600 MHz, mit Grafik & Dual Arm Cortex M4 für Infotainment & Kombiinstr DRA714 — SoC-Prozessor Arm Cortex-A15, 600 MHz, mit Grafik & DSP für Infotainment & Kombiinstrument DRA716 — SoC-Prozessor Arm Cortex-A15, 800 MHz, mit Grafik & DSP für Infotainment & Kombiinstrument DRA718 — SoC-Prozessor Arm Cortex-A15, 1 GHz, mit Grafik & DSP für Infotainment & Kombiinstrument DRA722 — SoC-Prozessor, 800 MHz, Arm Cortex-A15 mit Grafik und DSP für Infotainment & Cluster in Fahrzeugen DRA724 — SoC-Prozessor, 1 GHz, Arm Cortex-A15 mit Grafik und DSP für Infotainment & Cluster in Fahrzeugen DRA725 — SoC-Prozessor, 1,2 GHz, Arm Cortex-A15 mit Grafik und DSP für Infotainment & Cluster in Fahrzeugen DRA726 — Arm Cortex-A15, 1,5 GHz, mit Grafik & DSP für Infotainment & Kombiinstrument DRA746 — Dual-Arm Cortex-A15-SoC-Prozessor mit 1,5 GHz, Grafik und DSP für Fahrzeug-Infotainment und Cluster DRA74P — Multicore-SoC-Prozessoren mit ISP und pinkompatibel mit SoC-Prozessoren DRA74x DRA756 — Zweifacher 1,5 GHz A15, Dual EVE, Dual-DSP, erweiterter Peripherie SoC-Prozessor für Infotainment DRA75P — Multicore-SoC-Prozessoren mit ISP und pinkompatibel mit SoCs DRA75x für Infotainment-Anwendungen DRA76P — Hochleistungs-Multicore-SoC-Prozessoren mit ISP für digitale Cockpit-Anwendungen DRA77P — Hochleistungs-Multi-Core SoCs mit erweiterten Peripheriegeräten und ISP für digitale Cockpit-Anwendu DRA790 — SoC-Prozessor Arm Cortex-A15, 300 MHz, mit C66x-DSP, 500 MHz, für Audioverstärker DRA791 — SoC-Prozessor Arm Cortex-A15, 300 MHz, mit C66x-DSP, 750 MHz, für Audioverstärker DRA793 — SoC-Prozessor Arm Cortex-A15, 500 MHz, mit C66x-DSP, 750 MHz, für Audioverstärker DRA797 — SoC-Prozessor Arm Cortex-A15, 800 MHz, mit C66x-DSP, 750 MHz, für Audioverstärker
Digitale Signalprozessoren (DSPs)
DRA780 — SoC-Prozessor mit 500 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA781 — SoC-Prozessor mit 750 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA782 — SoC-Prozessor mit 2x 500 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA783 — SoC-Prozessor mit 2x 750 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA785 — SoC-Prozessor mit 2x 1000 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA786 — SoC-Prozessor mit 2x 500 MHz C66x DSP und 2 Dual-Arm Cortex-M4 & EVE für Audioverstärker DRA787 — SoC-Prozessor mit 2x 750 MHz C66x DSP und 2 Dual-Arm Cortex-M4 & EVE für Audioverstärker DRA788 — SoC-Prozessor mit 2x 1000 MHz C66x DSP und 1x EVE und 2 Dual Arm Cortex-M4 für Audioverstärker
Download-Optionen
Software-Entwicklungskit (SDK)

PROCESSOR-SDK-RTOS-AUTOMOTIVE-DRA7X

Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

Produkte
ARM-basierte Prozessoren
DRA710 — 600 MHz-Arm Cortex-A15-SoC-Prozessor mit Grafik für Infotainment und Cluster DRA712 — SoC-Prozessor Arm Cortex-A15, 600 MHz, mit Grafik & Dual Arm Cortex M4 für Infotainment & Kombiinstr DRA714 — SoC-Prozessor Arm Cortex-A15, 600 MHz, mit Grafik & DSP für Infotainment & Kombiinstrument DRA716 — SoC-Prozessor Arm Cortex-A15, 800 MHz, mit Grafik & DSP für Infotainment & Kombiinstrument DRA718 — SoC-Prozessor Arm Cortex-A15, 1 GHz, mit Grafik & DSP für Infotainment & Kombiinstrument DRA722 — SoC-Prozessor, 800 MHz, Arm Cortex-A15 mit Grafik und DSP für Infotainment & Cluster in Fahrzeugen DRA724 — SoC-Prozessor, 1 GHz, Arm Cortex-A15 mit Grafik und DSP für Infotainment & Cluster in Fahrzeugen DRA725 — SoC-Prozessor, 1,2 GHz, Arm Cortex-A15 mit Grafik und DSP für Infotainment & Cluster in Fahrzeugen DRA726 — Arm Cortex-A15, 1,5 GHz, mit Grafik & DSP für Infotainment & Kombiinstrument DRA74P — Multicore-SoC-Prozessoren mit ISP und pinkompatibel mit SoC-Prozessoren DRA74x DRA75P — Multicore-SoC-Prozessoren mit ISP und pinkompatibel mit SoCs DRA75x für Infotainment-Anwendungen DRA76P — Hochleistungs-Multicore-SoC-Prozessoren mit ISP für digitale Cockpit-Anwendungen DRA77P — Hochleistungs-Multi-Core SoCs mit erweiterten Peripheriegeräten und ISP für digitale Cockpit-Anwendu DRA790 — SoC-Prozessor Arm Cortex-A15, 300 MHz, mit C66x-DSP, 500 MHz, für Audioverstärker DRA791 — SoC-Prozessor Arm Cortex-A15, 300 MHz, mit C66x-DSP, 750 MHz, für Audioverstärker DRA793 — SoC-Prozessor Arm Cortex-A15, 500 MHz, mit C66x-DSP, 750 MHz, für Audioverstärker DRA797 — SoC-Prozessor Arm Cortex-A15, 800 MHz, mit C66x-DSP, 750 MHz, für Audioverstärker
Digitale Signalprozessoren (DSPs)
DRA780 — SoC-Prozessor mit 500 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA781 — SoC-Prozessor mit 750 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA782 — SoC-Prozessor mit 2x 500 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA783 — SoC-Prozessor mit 2x 750 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA785 — SoC-Prozessor mit 2x 1000 MHz C66x DSP und 2 Dual-Arm Cortex-M4 für Audioverstärker DRA786 — SoC-Prozessor mit 2x 500 MHz C66x DSP und 2 Dual-Arm Cortex-M4 & EVE für Audioverstärker DRA787 — SoC-Prozessor mit 2x 750 MHz C66x DSP und 2 Dual-Arm Cortex-M4 & EVE für Audioverstärker DRA788 — SoC-Prozessor mit 2x 1000 MHz C66x DSP und 1x EVE und 2 Dual Arm Cortex-M4 für Audioverstärker
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IDE, Konfiguration, Compiler oder Debugger

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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Betriebssystem (BS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
Von: Green Hills Software
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Support-Software

VCTR-3P-MICROSAR — Vector MICROSAR AUTOSAR-Software für Mikrocontroller und Hochleistungscomputer (HPCs)

Die MICROSAR- und DaVinci-Produktfamilien vereinfachen die Steuergeräte-Entwicklung mit ausgefeilter Embedded-Software und leistungsstarken Entwicklungswerkzeugen für Mikrocontroller und HPCs. Mit fortschrittlicher Infrastruktursoftware schaffen Sie eine optimale Basis für Ihre Steuergeräte und (...)
Von: Vector Informatik GmbH
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Simulationsmodell

DRA7xxP and TDA2Px BSDL Files

SPRM750.ZIP (34 KB) - BSDL Model
Herunterladen
Simulationsmodell

DRA7xxP and TDA2Px IBIS Files

SPRM748.ZIP (36622 KB) - IBIS Model
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Simulationsmodell

DRA7xxP and TDA2Px Thermal Model

SPRM749.ZIP (2 KB) - Thermal Model
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Berechnungstool

CLOCKTREETOOL — Taktbaum-Tool für Sitara, Automobilanwendungen, Sichtanalytik und digitale Signalprozessoren

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
Benutzerhandbuch: PDF
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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
FCCSP (ABZ) 760 Ultra Librarian
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