Gehäuseinformationen
| Gehäuse | Pins VQFN (RGC) | 64 |
| Betriebstemperaturbereich (°C) -40 to 85 |
| Gehäusemenge | Träger 250 | SMALL T&R |
Merkmale von LMK05028
- Two Independent PLL Channels Featuring:
- Jitter: 150-fs RMS for Outputs ≥ 100 MHz
- Phase Noise: –112 dBc/Hz at 100-Hz Offset for 122.88 MHz
- Hitless Switching: 50-ps Phase Transient With Phase Cancellation
- Programmable Loop Bandwidth With Fastlock
- Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
- Any Input to Any Output Frequency Translation
- Four Reference Clock
Inputs
- Priority-Based Input Selection
- Digital Holdover on Loss of Reference
- Eight Clock Outputs With
Programmable Drivers
- Up to Six Different Output Frequencies
- AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8-V or 2.5-V LVCMOS Output Formats
- EEPROM/ROM for Custom Clocks on Power-Up(2)
- Flexible Configuration Options
- 1 Hz (1 PPS) to 750 MHz on Input and Output
- XO: 10 to 100 MHz, TCXO: 10 to 54 MHz
- DCO Mode: < 1 ppt/Step for Fine Frequency and Phase Steering (IEEE 1588 Slave)
- Zero Delay for Deterministic Phase Offset
- Robust Clock Monitoring and Status
- I2C or SPI Interface
- Excellent Power Supply Noise Rejection (PSNR)
- 3.3-V Supply With 1.8-V, 2.5-V, or 3.3-V Outputs
- Industrial Temperature Range: –40°C to +85°C
Beschreibung von LMK05028
The LMK05028 is a high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The device’s low jitter and high PSNR reduce bit error rates (BER) in high-speed serial links.
The device has two PLL channels and generates up to eight output clocks with 150-fs RMS jitter. Each PLL domain can select from any four reference inputs to synchronize its outputs.
Each PLL channel supports programmable loop bandwidth for jitter and wander attenuation and fractional frequency translation for flexible frequency configuration. Synchronization options supported on each PLL channel includes hitless switching with phase cancellation, digital holdover, DCO mode with <1 ppt/step for precise clock steering (IEEE 1588 PTP slave), and zero-delay mode for deterministic input-to-output phase offset. The advanced reference input monitoring block ensures robust clock fault detection and helps to minimize output clock disturbance when a loss of reference (LOR) occurs.
The device can use a low-frequency TCXO/OCXO to determine the free-run or holdover frequency stability to maintain standards-compliant synchronization during LOR, or a standard XO when holdover frequency stability and wander are not critical. The device is fully programmable through I2C or SPI interface and supports custom frequency configuration on power-up with the internal EEPROM or ROM. The EEPROM is factory pre-programmable and in-system programmable.