Startseite Schnittstelle I2C & I3C ICs I2C Universal-I/OS (GPIOs)
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I2C & I3C ICs
I2C Universal-I/OS (GPIOs)

TCA6424A

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24-Bit-übersetzender 1,65- bis 5,5-V-I2C/SMBus-E/A-Expander mit Interrupt-, Reset- und Konfiguration

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Datenblatt

TCA6424A

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Produktdetails

Number of I/Os 24 Features Adjustable I/O level, Configuration registers, Interrupt pin, Reset pin Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Addresses 2 Rating Catalog Frequency (max) (MHz) 0.4 Operating temperature range (°C) -40 to 85
Number of I/Os 24 Features Adjustable I/O level, Configuration registers, Interrupt pin, Reset pin Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Addresses 2 Rating Catalog Frequency (max) (MHz) 0.4 Operating temperature range (°C) -40 to 85
UQFN (RGJ) 32 25 mm² 5 x 5
  • Operating power-supply voltage range of 1.65 V to 5.5 V
  • Allows bidirectional voltage-level translation and GPIO expansion between:
    • 1.8-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port
    • 2.5-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port
    • 3.3-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port
    • 5-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port
  • I2C to Parallel port expander
  • Low standby current consumption of 1 µA
  • Schmitt-Trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs
    • Vhys = 0.18 V Typ at 1.8 V
    • Vhys = 0.25 V Typ at 2.5 V
    • Vhys = 0.33 V Typ at 3.3 V
    • Vhys = 0.5 V Typ at 5 V
  • 5-V Tolerant I/O ports
  • Active-low reset input ( RESET)
  • Open-drain active-low interrupt output ( INT)
  • 400-kHz Fast I2C Bus
  • Input/output configuration register
  • Polarity inversion register
  • Internal power-on reset
  • Power up with all channels configured as inputs
  • No glitch on power up
  • Noise filter on SCL/SDA inputs
  • Latched outputs with high-current drive maximum capability for directly driving LEDs
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000-V Human-body model (A114-A)
    • 200-V Machine model (A115-A)
    • 1000-V Charged-device model (C101)
  • Operating power-supply voltage range of 1.65 V to 5.5 V
  • Allows bidirectional voltage-level translation and GPIO expansion between:
    • 1.8-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port
    • 2.5-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port
    • 3.3-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port
    • 5-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port
  • I2C to Parallel port expander
  • Low standby current consumption of 1 µA
  • Schmitt-Trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs
    • Vhys = 0.18 V Typ at 1.8 V
    • Vhys = 0.25 V Typ at 2.5 V
    • Vhys = 0.33 V Typ at 3.3 V
    • Vhys = 0.5 V Typ at 5 V
  • 5-V Tolerant I/O ports
  • Active-low reset input ( RESET)
  • Open-drain active-low interrupt output ( INT)
  • 400-kHz Fast I2C Bus
  • Input/output configuration register
  • Polarity inversion register
  • Internal power-on reset
  • Power up with all channels configured as inputs
  • No glitch on power up
  • Noise filter on SCL/SDA inputs
  • Latched outputs with high-current drive maximum capability for directly driving LEDs
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000-V Human-body model (A114-A)
    • 200-V Machine model (A115-A)
    • 1000-V Charged-device model (C101)

The bidirectional voltage level translation in the TCA6424A is provided through VCCI. VCCI should be connected to the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6424A. The voltage level on the P-port of the TCA6424A is determined by the VCCP.

The TCA6424A consists of three 8-bit Configuration (input or output selection), Input, Output, and Polarity Inversion (active high) registers. At power on, the I/Os are configured as inputs. However, the system controller can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system controller.

The system controller can reset the TCA6424A in the event of a timeout or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.

The TCA6424A open-drain interrupt ( INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system controller that an input state has changed.

INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA6424A can remain a simple target device.

The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low device current.

One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices to share the same I2C bus or SMBus.

The bidirectional voltage level translation in the TCA6424A is provided through VCCI. VCCI should be connected to the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6424A. The voltage level on the P-port of the TCA6424A is determined by the VCCP.

The TCA6424A consists of three 8-bit Configuration (input or output selection), Input, Output, and Polarity Inversion (active high) registers. At power on, the I/Os are configured as inputs. However, the system controller can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system controller.

The system controller can reset the TCA6424A in the event of a timeout or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.

The TCA6424A open-drain interrupt ( INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system controller that an input state has changed.

INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA6424A can remain a simple target device.

The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low device current.

One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices to share the same I2C bus or SMBus.
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Typ Titel Datum
* Data sheet TCA6424A Low-Voltage 24-Bit I2C and SMBus I/O Expander With Interrupt Output, Reset, and Configuration Registers datasheet (Rev. D) PDF | HTML 30 Jan 2023
Application note I2C: What is the Auto Increment Feature? PDF | HTML 05 Jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 Jul 2024
Application note I2C Dynamic Addressing 25 Apr 2019
Application note Choosing the Correct I2C Device for New Designs PDF | HTML 07 Sep 2016
Selection guide I2C Infographic Flyer 03 Dez 2015
Application note Understanding the I2C Bus PDF | HTML 30 Jun 2015
Application note I2C Bus Pull-Up Resistor Calculation PDF | HTML 13 Feb 2015
EVM User's guide I/O Expander EVM User's Guide (Rev. A) 25 Jul 2014

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