Produktdetails

DSP type 1 C64x DSP (max) (MHz) 513, 594, 810 CPU 32-/64-bit Operating system DSP/BIOS, Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) -40 to 105
DSP type 1 C64x DSP (max) (MHz) 513, 594, 810 CPU 32-/64-bit Operating system DSP/BIOS, Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) -40 to 105
NFBGA (ZWT) 361 256 mm² 16 x 16
  • High-Performance Digital Media SoC
    • 513-, 594-, 810-MHz C64x+™ Clock Rates
    • 256.5-, 297-, 405-MHz ARM926EJ-S™ Clock Rates
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4104, 4752, 6480 C64x+ MIPS
    • Fully Software-Compatible With C64x / ARM9™
    • Extended Temperature Devices Available
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle®: Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 16K-Byte RAM
    • 8K-Byte ROM
  • Embedded Trace Buffer™ (ETB11™) With 4KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Video Imaging Co-Processor (VICP)
  • Video Processing Subsystem
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Preview Engine for Real-Time Image Processing
      • Glueless Interface to Common Video Decoders
      • Histogram Module
      • Auto-Exposure, Auto-White Balance and Auto-Focus Module
      • Resize Engine Resize
        • Images From 1/4x to 4x
        • Separate Horizontal/Vertical Control
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Four 54-MHz DACs for a Combination of
        • Composite NTSC/PAL Video
        • Luma/Chroma Separate Video (S-video)
        • Component (YPbPr or RGB) Video (Progressive)
      • Digital Output
        • 8-/16-bit YUV or up to 24-Bit RGB
        • HD Resolution
        • Up to 2 Video Windows
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Up to 167-MHz Controller (A-513, -594)
      • Up to 189-MHz Controller (-810)
    • Asynchronous 16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Flash Card Interfaces
    • Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
    • Compact Flash Controller With True IDE Mode
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One with RTS and CTS Flow Control)
  • One Serial Peripheral Interface (SPI) With Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Audio Serial Port (ASP)
    • I2S
    • AC97 Audio Codec Interface
    • Standard Voice Codec Interface (AIC12)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
  • VLYNQ™ Interface (FPGA Interface)
  • Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed (480-Mbps) Client
    • USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
  • ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 361-Pin Pb-Free BGA Package(ZWT Suffix), 0.8-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (513, 594)
  • 3.3-V and 1.8-V I/O, 1.2-V DAC and USB, 1.3-V Internal (810 only)
  • Applications:
    • Digital Media
    • Networked Media Encode/Decode
    • Video Imaging

All other trademarks are the property of their respective owners

  • High-Performance Digital Media SoC
    • 513-, 594-, 810-MHz C64x+™ Clock Rates
    • 256.5-, 297-, 405-MHz ARM926EJ-S™ Clock Rates
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4104, 4752, 6480 C64x+ MIPS
    • Fully Software-Compatible With C64x / ARM9™
    • Extended Temperature Devices Available
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle®: Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 16K-Byte RAM
    • 8K-Byte ROM
  • Embedded Trace Buffer™ (ETB11™) With 4KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Video Imaging Co-Processor (VICP)
  • Video Processing Subsystem
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Preview Engine for Real-Time Image Processing
      • Glueless Interface to Common Video Decoders
      • Histogram Module
      • Auto-Exposure, Auto-White Balance and Auto-Focus Module
      • Resize Engine Resize
        • Images From 1/4x to 4x
        • Separate Horizontal/Vertical Control
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Four 54-MHz DACs for a Combination of
        • Composite NTSC/PAL Video
        • Luma/Chroma Separate Video (S-video)
        • Component (YPbPr or RGB) Video (Progressive)
      • Digital Output
        • 8-/16-bit YUV or up to 24-Bit RGB
        • HD Resolution
        • Up to 2 Video Windows
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Up to 167-MHz Controller (A-513, -594)
      • Up to 189-MHz Controller (-810)
    • Asynchronous 16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Flash Card Interfaces
    • Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
    • Compact Flash Controller With True IDE Mode
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One with RTS and CTS Flow Control)
  • One Serial Peripheral Interface (SPI) With Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Audio Serial Port (ASP)
    • I2S
    • AC97 Audio Codec Interface
    • Standard Voice Codec Interface (AIC12)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
  • VLYNQ™ Interface (FPGA Interface)
  • Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed (480-Mbps) Client
    • USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
  • ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 361-Pin Pb-Free BGA Package(ZWT Suffix), 0.8-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (513, 594)
  • 3.3-V and 1.8-V I/O, 1.2-V DAC and USB, 1.3-V Internal (810 only)
  • Applications:
    • Digital Media
    • Networked Media Encode/Decode
    • Video Imaging

All other trademarks are the property of their respective owners

The TMS320DM6446 (also referenced as DM6446) leverages TI's DaVinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates: A coprocessor 15 (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+™ DSP with added functionality and an expanded instruction set.

Any reference to the C64x™ DSP or C64x™ CPU also applies, unless otherwise noted, to the C64x+™ DSP and C64x+™ CPU, respectively.

With performance of up to 6480 million instructions per second (MIPS) at a clock rate of 810 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units--two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 3240 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 6480 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6446 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6446 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output with imaging co-processor (VICP) used for display.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV4:2:2. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6446. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644x and the network. The DM6446 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6446 to easily control peripheral devices and/or communicate with host processors. The DM6446 also provides multimedia card support, MMC/SD, with SDIO support.

The DM6446 also includes a Video/Imaging Co-processor (VICP) to offload many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. For more information on the VICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales representative.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides listed in Section 2.8.3.1, Related Documentation From Texas Instruments.

The DM6446 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320DM6446 (also referenced as DM6446) leverages TI's DaVinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates: A coprocessor 15 (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+™ DSP with added functionality and an expanded instruction set.

Any reference to the C64x™ DSP or C64x™ CPU also applies, unless otherwise noted, to the C64x+™ DSP and C64x+™ CPU, respectively.

With performance of up to 6480 million instructions per second (MIPS) at a clock rate of 810 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units--two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 3240 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 6480 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6446 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6446 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output with imaging co-processor (VICP) used for display.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV4:2:2. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6446. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644x and the network. The DM6446 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6446 to easily control peripheral devices and/or communicate with host processors. The DM6446 also provides multimedia card support, MMC/SD, with SDIO support.

The DM6446 also includes a Video/Imaging Co-processor (VICP) to offload many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. For more information on the VICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales representative.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides listed in Section 2.8.3.1, Related Documentation From Texas Instruments.

The DM6446 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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Typ Titel Datum
* Data sheet TMS320DM6446 Digital Media System-on-Chip datasheet (Rev. H) 30 Sep 2010
* Errata TMS320DM6446 Digital Media SoC Silicon Errata (Revs 2.3, 2.1, 1.3, 1.2 & 1.1) (Rev. N) 23 Jul 2010
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 24 Feb 2023
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) 21 Aug 2012
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) 21 Aug 2012
User guide Emulation and Trace Headers Technical Reference Manual (Rev. I) 09 Aug 2012
Application note Introduction to TMS320C6000 DSP Optimization 06 Okt 2011
User guide TMS320DM644x DMSoC 64-bit Timer User's Guide 01 Aug 2011
User guide TMS320C6000 Programmer's Guide (Rev. K) 11 Jul 2011
User guide TMS320DM644x DMSoC Inter-Integrated Circuit (I2C) Peripheral User's Guide (Rev. F) 25 Mär 2011
User guide TMS320DM644x DMSoC Video Processing Back End (VPBE) User's Guide (Rev. D) 27 Jan 2011
User guide TMS320DM644x DMSoC DDR2 Memory Controller User's Guide (Rev. E) 12 Jan 2011
User guide TMS320DM644x DMSoC EMAC/MDIO Module User's Guide (Rev. B) 23 Dez 2010
User guide TMS320DM644x DMSoC Video Processing Front End (VPFE) User's Guide (Rev. H) 25 Aug 2010
User guide TMS320DM644x DMSoC General-Purpose Input/Output (GPIO) User's Guide (Rev. A) 19 Aug 2010
Application note TMS320DM6446/3 Power Consumption Summary (Rev. B) 16 Aug 2010
User guide TMS320DM644x DMSoC Pulse-Width Modulator (PWM) User's Guide (Rev. A) 06 Aug 2010
User guide TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 03 Aug 2010
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30 Jul 2010
User guide TMS320DM644x DMSoC ARM Subsystem Reference Guide (Rev. C) 21 Jul 2010
Application note Migrating From TMS320DM6446 594 MHz to 810 MHz 20 Jul 2010
Application note Migrating From TMS320DM644x v.2.1 ROM Bootloader to 2.3 Version 20 Jul 2010
User guide TMS320DM644x DMSoC Universal Serial Bus (USB) Controller User's Guide (Rev. G) 02 Jun 2010
User guide TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) 18 Mär 2010
User guide TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) 18 Mär 2010
Application note USB Compliance Checklist (Rev. A) 10 Mär 2010
Application note Running a TMS320C64x+ Codec Across TMS320C64x+ Based DSP Platforms 24 Sep 2009
Application note Booting and Flashing via the DaVinci TMS320DM644x Serial Interface (Rev. A) 10 Sep 2009
Application note LSP 2.10 DaVinci Linux Drivers (Rev. A) 08 Jul 2009
Application note Common Object File Format (COFF) 15 Apr 2009
Application note Ultrasound Scan Conversion on TI's C64x+ DSPs 03 Apr 2009
User guide TMS320DM644x DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (Rev. C) 24 Feb 2009
User guide TMS320DM644x DMSoC Host Port Interface (HPI) User's Guide (Rev. B) 22 Feb 2009
User guide TMS320C64x+ DSP Cache User's Guide (Rev. B) 11 Feb 2009
Application note De-Interlacing and YUV 4:2:2 to 4:2:0 Conversion on DM6446 Using the Resizer (Rev. B) 17 Dez 2008
Application note Booting DaVinci EVM from NAND Flash (Rev. A) 15 Dez 2008
Application note 5 VIN solution using DCDC Controllers, a LDO, and a Digitally Prog. Sequencer 24 Nov 2008
Application note Migrating from TMS320DM6446 to TMS320DM6467 17 Nov 2008
White paper See the difference:DSPs in medical imaging 31 Okt 2008
More literature DaVinci Technology Overview Brochure (Rev. B) 27 Sep 2008
Application note Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) 21 Aug 2008
Application note Understanding the Davinci Preview Engine (Rev. A) 23 Jul 2008
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 17 Jul 2008
Application note Understanding the Davinci Resizer (Rev. B) 17 Jul 2008
Application note Implementing the DDR2 PCB Layout on the TMS320DM644x DMSoC (Rev. G) 16 Jun 2008
Application note Building a Small Embedded Linux Kernel Example (Rev. A) 27 Mai 2008
User guide TMS320DM644x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller UG (Rev. D) 27 Mai 2008
User guide TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) 15 Mai 2008
User guide TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) 15 Mai 2008
User guide TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) 05 Mai 2008
Application note TMS320DM644x Thermal Considerations (Rev. A) 23 Apr 2008
Application note TMS320DM6441 Power Consumption Summary Application Report 08 Apr 2008
User guide TMS320DM644x DMSoC Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. A) 08 Apr 2008
User guide TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) 06 Mär 2008
Application note Creating a TMS320DM6446 Audio Encode Example Using XDC Tools (Rev. A) 26 Feb 2008
User guide TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide (Rev. D) 25 Feb 2008
Application note Building GStreamer 11 Jan 2008
Application note Migrating from TMS320DM6446 to TMS320DM6437 05 Nov 2007
Application note Changing the DVEVM Memory Map 26 Sep 2007
User guide TMS320DM644x DMSoC VLYNQ Port User's Guide (Rev. A) 20 Sep 2007
User guide TMS320DM644x DMSoC Audio Serial Port (ASP) User's Guide (Rev. B) 17 Sep 2007
Application note Motion JPEG Demo on TMS320DM6446 (Rev. A) 11 Sep 2007
Application note Running Demo via ddd on the DVEVM 30 Jul 2007
Application note Using Static IP Between Linux Host and the DVEVM 30 Jul 2007
Application note Compact Flash (CF) Support on the DVEVM 25 Jul 2007
Application note Host USB Support on the DVEVM 20 Jul 2007
Application note Decode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 27 Jun 2007
Application note Digital Video Using DaVinci SoC 27 Jun 2007
Application note Encode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 27 Jun 2007
Application note EncodeDecode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 27 Jun 2007
Application note Measuring Video Quality With the TMS320DM6446 DVSDK 08 Mai 2007
User guide TMS320DM644x DMSoC Peripherals Overview Reference Guide (Rev. C) 18 Apr 2007
Product overview TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 04 Apr 2007
EVM User's guide TMS320DM644x DVEVM Windows CE v5.0 BSP Codec Engine User’s Guide 23 Mär 2007
EVM User's guide TMS320DM644x DVEVM Windows CE v5.0 Codec Engine Binary User's Guide 23 Mär 2007
Product overview DaVinci Technology - Digital Video Innovation Product Bulletin (Rev. D) 13 Feb 2007
More literature Overview of DaVinci™ TMS320DM644x Digital Media Portfolio (Rev. B) 13 Feb 2007
User guide TMS320DM644x DMSoC Serial Peripheral Interface (SPI) User's Guide (Rev. A) 07 Feb 2007
Application note DaVinci Technology Background and Specifications (Rev. A) 04 Jan 2007
Application note Basic Application Loading over the Serial Interface for the DaVinci TMS320DM644x 21 Dez 2006
Product overview Portable Media Player Based on DaVinci Technology 14 Nov 2006
Product overview Universal IP Player Solution from ATEME 02 Nov 2006
Application note DaVinci System Level Benchmarking Measurements 28 Sep 2006
Product overview DaVinci Benchmarks Product Bulletin (Rev. A) 12 Sep 2006
Application note Fast Development with DaVinci On Screen Display (OSD) 06 Jul 2006
User guide TMS320C64x+ DSP Big-Endian Library Programmer's Reference 10 Mär 2006
User guide TMS320C64x+ Image/Video Processing Library Programmer's Reference 10 Mär 2006
Application note Migrating from EDMA v2.0 to EDMA v3.0 for TMS320DM644X DMSoC 03 Dez 2005
User guide TMS320DM644x DMSoC ATA Controller User's Guide 03 Dez 2005
User guide TMS320DM644x DMSoC DSP Subsystem Reference Guide 03 Dez 2005
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 20 Okt 2005

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Debug-Tastkopf

TMDSADP — Adaptive Clocking-JTAG-Emulatoradapter

TMDSADP1420 adapter – used for connecting TI and 3rd party XDS510 and XDS560-class emulators with a 14 pin native connector to the TMDXEVM6446 or customer boards with a compact (CTI) 20-pin header. The adapter improves signal integrity, translates voltages, and can optionally provide adaptive (...)

Benutzerhandbuch: PDF
Debug-Tastkopf

TMDSEMU200-U — XDS200-USB-Debug-Tastkopf

Die XDS200 ist eine Debug-Sonde (Emulator) zum Debuggen von Embedded-Bausteinen von TI. Die XDS200 bietet ein ausgewogenes Preis-Leistungsverhältnis im Vergleich zum preiswerten XDS110 und dem leistungsstarken XDS560v2 und unterstützt zahlreiche Standards (IEEE1149,1, IEEE1149,7, SWD) in einem (...)

Debug-Tastkopf

TMDSEMU560V2STM-U — XDS560v2 System-Trace-USB-Debug-Tastkopf

Der XDS560v2 ist die leistungsstärkste Debug-Sonde aus der XDS560™ Familie von Debug-Sonden und unterstützt sowohl den traditionellen JTAG-Standard (IEEE1149.1) als auch cJTAG (IEEE1149.7).  Bitte beachten: Diese Lösung unterstützt kein Serial Wire Debug (SWD).

Alle XDS-Debug-Tastköpfe unterstützen (...)

Debug-Tastkopf

TMDSEMU560V2STM-UE — XDS560v2 System-Trace-USB-und Ethernet-Debug-Tastkopf

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

Software-Entwicklungskit (SDK)

LINUXDVSDK-DV — Linux Digital Video Software Development Kit (DVSDK) v2x/v3x – DaVinci-Digitalmedienprozessoren

Effective Oct 2010 - Linux DVSDK v4 has been released. For DaVinci™ devices not listed above, search TI.com for your device part number; This product page will have a link to your current DVSDK.

The Linux™ Digital Video Software Development Kits (DVSDKs) enable DaVinci system integrators to (...)

Anwendungssoftware und Frameworks

TMDMFP — Multimedia-Framework-Produkte (MFP) – Codec-Engine, Framework-Komponenten und XDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable signal processors over fixed-function devices is their ability to accelerate multiple multimedia functions and provide flexible environments to enable user customization. However, sharing scarce embedded hardware resources between (...)

Benutzerhandbuch: PDF
Treiber oder Bibliothek

SPRC122 C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

Produkte
Digitale Signalprozessoren (DSPs)
SM320C6201-EP Optimierter Festkomma-DSP C6201 SM320C6455-EP Verbessertes Produkt, C6455 Festkomma-DSP SMJ320C6201B Digitaler Festkomma-Signalprozessor, Militäranwendungen SMJ320C6203 C62x Festkomma-DSP in militärischer Qualität – Keramikgehäuse TMS320C6202B C62x Festkomma-DSP – bis zu 300 MHz, 384 KB TMS320C6203B C62x Festkomma-DSP – bis zu 300 MHz, 896 KB TMS320C6204 Digitaler Festkomma-Signalprozessor TMS320C6205 Digitaler Festkomma-Signalprozessor TMS320C6211B C62x Festkomma-DSP – bis zu 167MHz TMS320C6412 C64x Festkomma-DSP – bis zu 720 MHz, McBSP, McASP, I2cC, Ethernet TMS320C6414 C64x Festkomma-DSP – bis zu 720MHz, McBSP TMS320C6414T C64x Festkomma-DSP – bis zu 1GHz, McBSP TMS320C6415 C64x Festkomma-DSP – bis zu 720MHz, McBSP, PCI TMS320C6415T C64x Festkomma-DSP – bis zu 850MHz, McBSP, PCI TMS320C6416 C64x Festkomma-DSP – bis zu 720MHz, McBSP, PCI, VCP/TCP TMS320C6416T C64x Festkomma-DSP – bis zu 850MHz, McBSP, PCI, VCP/TCP TMS320C6421 C64x+ Festkomma-DSP – bis zu 600 MHz, 8 Bit EMIFA, 16-Bit DDR2, SDRAM TMS320C6421Q C64x+ Festkomma-DSP – bis zu 600 MHz, 8 Bit EMIFA, 16-Bit DDR2 TMS320C6424 C64x+ Festkomma-DSP – bis zu 600 MHz, 16/8 Bit EMIFA, 32/16 Bit DDR2, SDRAM TMS320C6424Q C64x+ Festkomma-DSP – bis zu 600 MHz, 16/8-Bit EMIFA, 32/16 Bit DDR2 TMS320C6452 C64x+ Festkomma-DSP – bis zu 900 MHz, 1 Gbps-Ethernet TMS320C6454 C64x+ Festkomma-DSP – bis zu 1 GHz, 64-Bit EMIFA, 32/16 Bit DDR2, 1 Gbps-Ethernet TMS320C6455 C64x+ Festkomma-DSP – bis zu 1,2 GHz, 64-Bit EMIFA, 32/16 Bit DDR2, Ethernet 1Gbit/s TMS320C6457 Digitaler Signalprozessor für die Kommunikationsinfrastruktur TMS320C6474 Digitaler Signalprozessor mit mehreren Kernen TMS320DM640 Digitaler Festkomma-Signalprozessor für Video/Bildgebung TMS320DM641 Digitaler Festkomma-Signalprozessor für Video/Bildgebung TMS320DM642 Digitaler Festkomma-Signalprozessor für Video/Bildgebung TMS320DM642Q Digitaler Festkomma-Signalprozessor für Video/Bildgebung TMS320DM6431 Digitaler Medienprozessor TMS320DM6431Q Digitaler Medienprozessor, bis zu 2400 MIPS, 300-MHz-Taktrate TMS320DM6433 Digitaler Medienprozessor TMS320DM6435 Digitaler Medienprozessor TMS320DM6435Q Digitaler Medienprozessor, bis zu 4800 MIPS, 600-MHz-Taktrate, 1 McASP, 1 McBSP TMS320DM6437 Digitaler Medienprozessor TMS320DM6437Q Digitaler Medienprozessor, bis zu 4800 MIPS, 600-MHz-Taktrate, 1 McASP, 2 McBSP TMS320DM6441 DaVinci Digital-Media-System-on-Chip TMS320DM6443 DaVinci Digital-Media-System-on-Chip TMS320DM6446 DaVinci Digital-Media-System-on-Chip
Treiber oder Bibliothek

SPRC831 — Video Imaging Co-Processor (VICP)-Signalverarbeitungsbibliothek

Texas Instruments VICP Signal processing library is a collection of highly tuned SW algorithms that execute on the VICP H/W accelerator. The library allows the application developer to effectively utilize the VICP performance without spending significant time in developing software for the (...)
Benutzerhandbuch: PDF
Treiber oder Bibliothek

TELECOMLIB — Telekommunikations- und Medienbibliotheken – FAXLIB, VoLIB und AEC/AER für TMS320C64x+ und TMS320C55

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
Software-Codec

C64XPLUSCODECS — CODECS – Video und Sprache – C64x+-basierte Geräte (OMAP35x, C645x, C647x, DM646, DM644x, DM643x)

Die TI-Codecs sind kostenlos, werden mit Produktionslizenzen geliefert und stehen ab sofort zum Download bereit. Alle Codecs wurden eingehend geprüft und lassen sich problemlos in Video- und Sprachanwendungen integrieren. Klicken Sie auf die Schaltfläche „GET SOFTWARE“ (oben), um auf die neuesten, (...)
Software-Codec

DM644XCODECS Codecs for DM644x - Software and Documentation

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

Produkte
Digitale Signalprozessoren (DSPs)
SM320DM6446-HIREL Hochzuverlässiges Produkt, Digital-Media-Prozessor DM6446 TMS320DM6441 DaVinci Digital-Media-System-on-Chip TMS320DM6443 DaVinci Digital-Media-System-on-Chip TMS320DM6446 DaVinci Digital-Media-System-on-Chip
Download-Optionen
Software-Codec

TMDXDAISXDM — eXpressDSP Algorithm Standard – xDAIS-Entwicklungskit und XDM

xDAIS and xDM

The eXpressDSP™ Algorithm Interoperability Standard (xDAIS) and the eXpressDSP Digital Media (xDM) standard fully leverage the ability of DSPs to perform a wide range of multimedia functions on a single device. eXpressDSP compliance is achieved by adhering to these standards. To (...)

Benutzerhandbuch: PDF
Simulationsmodell

DM6446 ZWT BSDL Model

SPRM203.ZIP (10 KB) - BSDL Model
Simulationsmodell

DM6446 ZWT BSDL version 2.1 Model (Rev. A)

SPRM325A.ZIP (8 KB) - BSDL Model
Simulationsmodell

DM6446 ZWT IBIS Model (Rev. C)

SPRM202C.ZIP (112 KB) - IBIS Model
Simulationsmodell

DM6446_DDR2 ZWT IBIS Model

SPRM450.ZIP (50 KB) - IBIS Model
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
NFBGA (ZWT) 361 Ultra Librarian

Bestellen & Qualität

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  • RoHS
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  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
  • Werksstandort
  • Montagestandort

Empfohlene Produkte können Parameter, Evaluierungsmodule oder Referenzdesigns zu diesem TI-Produkt beinhalten.

Support und Schulungen

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