Produktdetails

DSP type 1 C64x DSP (max) (MHz) 400, 500, 600, 700 CPU 32-/64-bit Operating system DSP/BIOS, VLX Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) 0 to 90
DSP type 1 C64x DSP (max) (MHz) 400, 500, 600, 700 CPU 32-/64-bit Operating system DSP/BIOS, VLX Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) 0 to 90
BGA (ZDU) 376 529 mm² 23 x 23 NFBGA (ZWT) 361 256 mm² 16 x 16
  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media Processor (DM6433)
    • 2.5-, 2-, 1.67, 1.51-, 1.43-ns Instruction Cycle Time
    • 400-, 500-, 600-, 660-, 700-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 3200, 4000, 4800, 5280, 5600 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix) Grades
    • Low-Power Device (L suffix)
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
    • C64x+ Instruction Set Features
      • Byte-Addressable (8-/16-/32-/64-Bit Data)
      • 8-Bit Overflow Protection
      • Bit-Field Extract, Set, Clear
      • Normalization, Saturation, Bit-Counting
      • VelociTI.2 Increased Orthogonality
      • C64x+ Extensions
        • Compact 16-bit Instructions
        • Additional Instructions to Support Complex Multiplies
    • C64x+ L1/L2 Memory Architecture
      • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
      • 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
      • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
    • Supports Little Endian Mode Only
    • Video Processing Subsystem (VPSS)
      • Front End Provides (Resizer Only):
        • Resize Images From 1/4× to 4×
        • Separate Horizontal and Vertical Control
      • Back End Provides:
        • Hardware On-Screen Display (OSD)
        • Four 54-MHz DACs for a Combination of
          • Composite NTSC/PAL Video
          • Luma/Chroma Separate Video (S-video)
          • Component (YPbPr or RGB) Video (Progressive)
        • Digital Output
          • 8-/16-bit YUV or up to 24-Bit RGB
          • HD Resolution
          • Up to 2 Video Windows
    • External Memory Interfaces (EMIFs)
      • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
        • Supports up to 333-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
      • Asynchronous 8-Bit Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
        • Flash Memory Interfaces
          • NOR (8-Bit-Wide Data)
          • NAND (8-Bit-Wide Data)
    • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
    • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
    • One 64-Bit Watch Dog Timer
    • One UART With RTS and CTS Flow Control
    • Master/Slave Inter-Integrated Circuit (I2C Bus™)
    • One Multichannel Buffered Serial Port (McBSP0)
      • I2S and TDM
      • AC97 Audio Codec Interface
      • SPI
      • Standard Voice Codec Interface (AIC12)
      • Telecom Interfaces - ST-Bus, H-100
      • 128 Channel Mode
    • Multichannel Audio Serial Port (McASP0)
      • Four Serializers and SPDIF (DIT) Mode
    • 16-Bit Host-Port Interface (HPI)
    • 32-Bit 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface
    • 10/100 Mb/s Ethernet MAC (EMAC)
      • IEEE 802.3 Compliant
      • Supports Media Independent Interface (MII)
      • Management Data I/O (MDIO) Module
    • VLYNQ™ Interface (FPGA Interface)
    • Three Pulse Width Modulator (PWM) Outputs
    • On-Chip ROM Bootloader
    • Individual Power-Savings Modes
    • Flexible PLL Clock Generators
    • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
    • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
    • Packages:
      • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
      • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
    • 0.09-µm/6-Level Cu Metal Process (CMOS)
    • 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-L/-Q6/-5Q/-4Q)
    • 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
    • Applications:
      • Digital Media
      • Networked Media Decode

All trademarks are the property of their respective owners.

  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media Processor (DM6433)
    • 2.5-, 2-, 1.67, 1.51-, 1.43-ns Instruction Cycle Time
    • 400-, 500-, 600-, 660-, 700-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 3200, 4000, 4800, 5280, 5600 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix) Grades
    • Low-Power Device (L suffix)
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
    • C64x+ Instruction Set Features
      • Byte-Addressable (8-/16-/32-/64-Bit Data)
      • 8-Bit Overflow Protection
      • Bit-Field Extract, Set, Clear
      • Normalization, Saturation, Bit-Counting
      • VelociTI.2 Increased Orthogonality
      • C64x+ Extensions
        • Compact 16-bit Instructions
        • Additional Instructions to Support Complex Multiplies
    • C64x+ L1/L2 Memory Architecture
      • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
      • 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
      • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
    • Supports Little Endian Mode Only
    • Video Processing Subsystem (VPSS)
      • Front End Provides (Resizer Only):
        • Resize Images From 1/4× to 4×
        • Separate Horizontal and Vertical Control
      • Back End Provides:
        • Hardware On-Screen Display (OSD)
        • Four 54-MHz DACs for a Combination of
          • Composite NTSC/PAL Video
          • Luma/Chroma Separate Video (S-video)
          • Component (YPbPr or RGB) Video (Progressive)
        • Digital Output
          • 8-/16-bit YUV or up to 24-Bit RGB
          • HD Resolution
          • Up to 2 Video Windows
    • External Memory Interfaces (EMIFs)
      • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
        • Supports up to 333-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
      • Asynchronous 8-Bit Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
        • Flash Memory Interfaces
          • NOR (8-Bit-Wide Data)
          • NAND (8-Bit-Wide Data)
    • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
    • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
    • One 64-Bit Watch Dog Timer
    • One UART With RTS and CTS Flow Control
    • Master/Slave Inter-Integrated Circuit (I2C Bus™)
    • One Multichannel Buffered Serial Port (McBSP0)
      • I2S and TDM
      • AC97 Audio Codec Interface
      • SPI
      • Standard Voice Codec Interface (AIC12)
      • Telecom Interfaces - ST-Bus, H-100
      • 128 Channel Mode
    • Multichannel Audio Serial Port (McASP0)
      • Four Serializers and SPDIF (DIT) Mode
    • 16-Bit Host-Port Interface (HPI)
    • 32-Bit 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface
    • 10/100 Mb/s Ethernet MAC (EMAC)
      • IEEE 802.3 Compliant
      • Supports Media Independent Interface (MII)
      • Management Data I/O (MDIO) Module
    • VLYNQ™ Interface (FPGA Interface)
    • Three Pulse Width Modulator (PWM) Outputs
    • On-Chip ROM Bootloader
    • Individual Power-Savings Modes
    • Flexible PLL Clock Generators
    • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
    • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
    • Packages:
      • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
      • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
    • 0.09-µm/6-Level Cu Metal Process (CMOS)
    • 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-L/-Q6/-5Q/-4Q)
    • 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
    • Applications:
      • Digital Media
      • Networked Media Decode

All trademarks are the property of their respective owners.

The TMS320C64x+™ DSPs (including the TMS320DM6433 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6433 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6433 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6433 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space-384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP0); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; a UART with hardware handshaking support; 3 pulse width modulator (PWM) peripherals; 1 peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6433 device includes a Video Processing Subsystem (VPSS) with a Video Processing Back-End (VPBE) output.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6433 and the network. The DM6433 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow DM6433 to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6433 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

The TMS320C64x+™ DSPs (including the TMS320DM6433 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6433 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6433 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6433 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space-384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP0); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; a UART with hardware handshaking support; 3 pulse width modulator (PWM) peripherals; 1 peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6433 device includes a Video Processing Subsystem (VPSS) with a Video Processing Back-End (VPBE) output.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6433 and the network. The DM6433 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow DM6433 to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6433 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

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Technische Dokumentation

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Typ Titel Datum
* Data sheet TMS320DM6433 Digital Media Processor datasheet (Rev. C) 06 Jun 2008
* Errata TMS320DM6437/35/33/31 DMP Silicon Errata (Revs. 1.3 1.2 1.1 & 1.0) (Rev. E) 12 Aug 2011
Application note Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 13 Aug 2015
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) 21 Aug 2012
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) 21 Aug 2012
Application note Using the TMS320DM643x Bootloader (Rev. E) 23 Mär 2012
Application note Introduction to TMS320C6000 DSP Optimization 06 Okt 2011
User guide TMS320C6000 Programmer's Guide (Rev. K) 11 Jul 2011
User guide TMS320DM643x DMP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. E) 25 Mär 2011
User guide TMS320DM643x DMP DDR2 Memory Controller User's Guide (Rev. C) 12 Jan 2011
User guide TMS320DM643x DMP EMAC/MDIO User's Guide (Rev. C) 23 Dez 2010
User guide TMS320DM643x DMP Pulse-Width Modulator (PWM) User's Guide (Rev. B) 05 Aug 2010
User guide TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 03 Aug 2010
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30 Jul 2010
User guide TMS320DM643x DMP Peripheral Component Interconnect (PCI) User's Guide (Rev. C) 14 Mai 2010
Application note TMS320DM643x Power Consumption Summary (Rev. C) 10 Mai 2010
User guide TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) 18 Mär 2010
User guide TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) 18 Mär 2010
User guide TMS320DM643x DMP Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. C) 16 Dez 2009
Application note Common Object File Format (COFF) 15 Apr 2009
User guide TMS320DM643x DMP Asynchronous External Memory Interface (EMIF) UG (Rev. B) 24 Feb 2009
User guide TMS320C64x+ DSP Cache User's Guide (Rev. B) 11 Feb 2009
Application note 12Vin DM643x Power using Integrated-FET DC/DC Converters and LDO 09 Okt 2008
Application note 5Vin DM643x Power using DC/DC Controllers and LDO 09 Okt 2008
Application note 5Vin DM643x Power using Integrated-FET DC/DC Converters and LDO 09 Okt 2008
Application note 5Vin DM643x Power using a PMIC (Multi-output DC/DC Converter) 09 Okt 2008
Application note Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) 21 Aug 2008
Application note Understanding the Davinci Preview Engine (Rev. A) 23 Jul 2008
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 17 Jul 2008
Application note Understanding the Davinci Resizer (Rev. B) 17 Jul 2008
User guide TMS320DM643x DMP Host Port Interface (HPI) User's Guide (Rev. D) 16 Jul 2008
Application note Implementing DDR2 PCB Layout on the TMS320DM643x DMSoC (Rev. A) 26 Jun 2008
Application note How to Use the EDMA3 Driver on a TMS320DM643x Device (Rev. A) 16 Jun 2008
User guide TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) 15 Mai 2008
User guide TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) 15 Mai 2008
User guide TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) 05 Mai 2008
User guide TMS320DM643x DMP General-Purpose Input/Output (GPIO) User's Guide (Rev. B) 18 Mär 2008
User guide TMS320DM643x DMP Multichannel Audio Serial Port (McASP) User's Guide (Rev. D) 13 Mär 2008
User guide TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) 06 Mär 2008
User guide TMS320DM643x DMP Enhanced DMA (EDMA) Controller User's Guide (Rev. A) 03 Mär 2008
User guide TMS320DM643x DMP DSP Subsystem Reference Guide (Rev. E) 05 Feb 2008
User guide TMS320DM643x DMP Video Processing Back End (VPBE) User's Guide (Rev. A) 18 Dez 2007
Application note How to Use the VPBE and VPFE Driver on the TMS320DM643x Devices (Rev. A) 14 Nov 2007
User guide TMS320DM643x DMP VLYNQ Port User's Guide (Rev. B) 20 Sep 2007
User guide TMS320DM643x DMP Multichannel Buffered Serial Port (McBSP) User's Guide (Rev. C) 17 Sep 2007
Application note TMS320DM643x Pin Multiplexing Utility 06 Jul 2007
User guide TMS320DM643x DMP Peripherals Overview Reference Guide (Rev. A) 25 Jun 2007
Product overview TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 04 Apr 2007
Product overview DaVinci Technology - Digital Video Innovation Product Bulletin (Rev. D) 13 Feb 2007
More literature Overview of DaVinci™ TMS320DM643x Digital Media Portfolio (Rev. B) 13 Feb 2007
Application note DaVinci Technology Background and Specifications (Rev. A) 04 Jan 2007
User guide TMS320DM643x DMP 64-Bit Timer User's Guide 18 Dez 2006
User guide TMS320C64x+ DSP Big-Endian Library Programmer's Reference 10 Mär 2006
User guide TMS320C64x+ Image/Video Processing Library Programmer's Reference 10 Mär 2006
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 20 Okt 2005

Design und Entwicklung

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Debug-Tastkopf

TMDSEMU200-U — XDS200-USB-Debug-Tastkopf

Die XDS200 ist eine Debug-Sonde (Emulator) zum Debuggen von Embedded-Bausteinen von TI. Die XDS200 bietet ein ausgewogenes Preis-Leistungsverhältnis im Vergleich zum preiswerten XDS110 und dem leistungsstarken XDS560v2 und unterstützt zahlreiche Standards (IEEE1149,1, IEEE1149,7, SWD) in einem (...)

Debug-Tastkopf

TMDSEMU560V2STM-U — XDS560v2 System-Trace-USB-Debug-Tastkopf

Der XDS560v2 ist die leistungsstärkste Debug-Sonde aus der XDS560™ Familie von Debug-Sonden und unterstützt sowohl den traditionellen JTAG-Standard (IEEE1149.1) als auch cJTAG (IEEE1149.7).  Bitte beachten: Diese Lösung unterstützt kein Serial Wire Debug (SWD).

Alle XDS-Debug-Tastköpfe unterstützen (...)

Debug-Tastkopf

TMDSEMU560V2STM-UE — XDS560v2 System-Trace-USB-und Ethernet-Debug-Tastkopf

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

Anwendungssoftware und Frameworks

TMDMFP — Multimedia-Framework-Produkte (MFP) – Codec-Engine, Framework-Komponenten und XDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable signal processors over fixed-function devices is their ability to accelerate multiple multimedia functions and provide flexible environments to enable user customization. However, sharing scarce embedded hardware resources between (...)

Benutzerhandbuch: PDF
Treiber oder Bibliothek

SPRC122 C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

Produkte
Digitale Signalprozessoren (DSPs)
SM320C6201-EP Optimierter Festkomma-DSP C6201 SM320C6455-EP Verbessertes Produkt, C6455 Festkomma-DSP SMJ320C6201B Digitaler Festkomma-Signalprozessor, Militäranwendungen SMJ320C6203 C62x Festkomma-DSP in militärischer Qualität – Keramikgehäuse TMS320C6202B C62x Festkomma-DSP – bis zu 300 MHz, 384 KB TMS320C6203B C62x Festkomma-DSP – bis zu 300 MHz, 896 KB TMS320C6204 Digitaler Festkomma-Signalprozessor TMS320C6205 Digitaler Festkomma-Signalprozessor TMS320C6211B C62x Festkomma-DSP – bis zu 167MHz TMS320C6412 C64x Festkomma-DSP – bis zu 720 MHz, McBSP, McASP, I2cC, Ethernet TMS320C6414 C64x Festkomma-DSP – bis zu 720MHz, McBSP TMS320C6414T C64x Festkomma-DSP – bis zu 1GHz, McBSP TMS320C6415 C64x Festkomma-DSP – bis zu 720MHz, McBSP, PCI TMS320C6415T C64x Festkomma-DSP – bis zu 850MHz, McBSP, PCI TMS320C6416 C64x Festkomma-DSP – bis zu 720MHz, McBSP, PCI, VCP/TCP TMS320C6416T C64x Festkomma-DSP – bis zu 850MHz, McBSP, PCI, VCP/TCP TMS320C6421 C64x+ Festkomma-DSP – bis zu 600 MHz, 8 Bit EMIFA, 16-Bit DDR2, SDRAM TMS320C6421Q C64x+ Festkomma-DSP – bis zu 600 MHz, 8 Bit EMIFA, 16-Bit DDR2 TMS320C6424 C64x+ Festkomma-DSP – bis zu 600 MHz, 16/8 Bit EMIFA, 32/16 Bit DDR2, SDRAM TMS320C6424Q C64x+ Festkomma-DSP – bis zu 600 MHz, 16/8-Bit EMIFA, 32/16 Bit DDR2 TMS320C6452 C64x+ Festkomma-DSP – bis zu 900 MHz, 1 Gbps-Ethernet TMS320C6454 C64x+ Festkomma-DSP – bis zu 1 GHz, 64-Bit EMIFA, 32/16 Bit DDR2, 1 Gbps-Ethernet TMS320C6455 C64x+ Festkomma-DSP – bis zu 1,2 GHz, 64-Bit EMIFA, 32/16 Bit DDR2, Ethernet 1Gbit/s TMS320C6457 Digitaler Signalprozessor für die Kommunikationsinfrastruktur TMS320C6474 Digitaler Signalprozessor mit mehreren Kernen TMS320DM640 Digitaler Festkomma-Signalprozessor für Video/Bildgebung TMS320DM641 Digitaler Festkomma-Signalprozessor für Video/Bildgebung TMS320DM642 Digitaler Festkomma-Signalprozessor für Video/Bildgebung TMS320DM642Q Digitaler Festkomma-Signalprozessor für Video/Bildgebung TMS320DM6431 Digitaler Medienprozessor TMS320DM6431Q Digitaler Medienprozessor, bis zu 2400 MIPS, 300-MHz-Taktrate TMS320DM6433 Digitaler Medienprozessor TMS320DM6435 Digitaler Medienprozessor TMS320DM6435Q Digitaler Medienprozessor, bis zu 4800 MIPS, 600-MHz-Taktrate, 1 McASP, 1 McBSP TMS320DM6437 Digitaler Medienprozessor TMS320DM6437Q Digitaler Medienprozessor, bis zu 4800 MIPS, 600-MHz-Taktrate, 1 McASP, 2 McBSP TMS320DM6441 DaVinci Digital-Media-System-on-Chip TMS320DM6443 DaVinci Digital-Media-System-on-Chip TMS320DM6446 DaVinci Digital-Media-System-on-Chip
Treiber oder Bibliothek

TELECOMLIB — Telekommunikations- und Medienbibliotheken – FAXLIB, VoLIB und AEC/AER für TMS320C64x+ und TMS320C55

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
Software-Codec

TMDXDAISXDM — eXpressDSP Algorithm Standard – xDAIS-Entwicklungskit und XDM

xDAIS and xDM

The eXpressDSP™ Algorithm Interoperability Standard (xDAIS) and the eXpressDSP Digital Media (xDM) standard fully leverage the ability of DSPs to perform a wide range of multimedia functions on a single device. eXpressDSP compliance is achieved by adhering to these standards. To (...)

Benutzerhandbuch: PDF
Simulationsmodell

DM6433 ZDU BSDL Model (Rev. A)

SPRM229A.ZIP (10 KB) - BSDL Model
Simulationsmodell

DM6433 ZDU IBIS Model (Rev. B)

SPRM235B.ZIP (267 KB) - IBIS Model
Simulationsmodell

DM6433 ZWT BSDL Model (Rev. A)

SPRM228A.ZIP (10 KB) - BSDL Model
Simulationsmodell

DM6433 ZWT IBIS Model (Rev. B)

SPRM234B.ZIP (267 KB) - IBIS Model
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
BGA (ZDU) 376 Ultra Librarian
NFBGA (ZWT) 361 Ultra Librarian

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