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Interruptores y multiplexores
Demultiplexores y decodificadores digitales

SN54HC138-SP

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Descodificadores/desmultiplexores de 3 a 8 líneas

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SN54HC138-SP

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Detalles del producto

Technology family HC Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Space Supply current (max) (µA) 160
Technology family HC Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Space Supply current (max) (µA) 160
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 CFP (W) 16 69.319 mm² 10.3 x 6.73
  • Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Wide Operating Voltage Range (2 V to 6 V)
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Maximum ICC
  • Typical tpd = 15 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1-µA Maximum
  • Active Low Outputs ( Selected Output is Low)
  • Incorporate Three Enable Inputs to Simplify Cascading or Data Reception
  • Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Wide Operating Voltage Range (2 V to 6 V)
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Maximum ICC
  • Typical tpd = 15 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1-µA Maximum
  • Active Low Outputs ( Selected Output is Low)
  • Incorporate Three Enable Inputs to Simplify Cascading or Data Reception

The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
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Documentación técnica

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* Data sheet SNx4HC138 3-Line To 8-Line Decoders/Demultiplexers datasheet (Rev. G) PDF | HTML 08 oct 2021

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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