Inicio Interruptores y multiplexores Interruptores y multiplexores analógicos
Inicio
Interruptores y multiplexores
Interruptores y multiplexores analógicos

SN74CBTLV3857

ACTIVO

Interruptor de bus FET de 3.3 V, 1:1 (SPST) y 10 canales con resistores de bajada internos

Haga su pedido ahora
Hoja de datos

SN74CBTLV3857

ACTIVO
Hoja de datos Haga su pedido ahora

Detalles del producto

Configuration 1:1 SPST Number of channels 10 Power supply voltage - single (V) 3.3 Protocols Analog Ron (typ) (Ω) 5 ON-state leakage current (max) (µA) 1000 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 85 Features Powered-off protection Input/output continuous current (max) (mA) 48 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
Configuration 1:1 SPST Number of channels 10 Power supply voltage - single (V) 3.3 Protocols Analog Ron (typ) (Ω) 5 ON-state leakage current (max) (µA) 1000 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 85 Features Powered-off protection Input/output continuous current (max) (mA) 48 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • Enable Signal Is SSTL_2 Compatible
  • Flow-Through Architecture Optimizes PCB Layout
  • Designed for Use With 200 Mbit/s Double Data-Rate (DDR) SDRAM Applications
  • Switch On-State Resistance Is Designed to Eliminate Series Resistor to DDR SDRAM
  • Internal 10-k Pulldown Resistors to Ground on B Port
  • Internal 50-k Pullup Resistor on Output-Enable Input
  • Rail-to-Rail Switching on Data I/O Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Enable Signal Is SSTL_2 Compatible
  • Flow-Through Architecture Optimizes PCB Layout
  • Designed for Use With 200 Mbit/s Double Data-Rate (DDR) SDRAM Applications
  • Switch On-State Resistance Is Designed to Eliminate Series Resistor to DDR SDRAM
  • Internal 10-k Pulldown Resistors to Ground on B Port
  • Internal 50-k Pullup Resistor on Output-Enable Input
  • Rail-to-Rail Switching on Data I/O Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

This 10-bit FET bus switch is designed for 3-V to 3.6-V VCC operation and SSTL_2 output-enable (OE\) input levels.

When OE\ is low, the 10-bit bus switch is on, and port A is connected to port B. When OE\ is high, the switch is open, and the high-impedance state exists between the two ports. There are 10-k pulldown resistors to ground on the B port.

The FET switch on-state resistance is designed to replace the series terminating resistor in the SSTL_2 data path.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

This 10-bit FET bus switch is designed for 3-V to 3.6-V VCC operation and SSTL_2 output-enable (OE\) input levels.

When OE\ is low, the 10-bit bus switch is on, and port A is connected to port B. When OE\ is high, the switch is open, and the high-impedance state exists between the two ports. There are 10-k pulldown resistors to ground on the B port.

The FET switch on-state resistance is designed to replace the series terminating resistor in the SSTL_2 data path.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.
filter Buscar otro/a Interruptores y multiplexores analógicos
Descargar Ver vídeo con transcripción Video

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 18
Tipo Título Fecha
* Data sheet SN74CBTLV3857 datasheet (Rev. E) 13 oct 2003
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 02 jun 2022
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 01 dic 2021
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 06 ene 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 jul 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note How to Select Little Logic (Rev. A) 26 jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
More literature Digital Bus Switch Selection Guide (Rev. A) 10 nov 2004
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note Bus FET Switch Solutions for Live Insertion Applications 07 feb 2003
Application note Texas Instruments Little Logic Application Report 01 nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
User guide CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) 01 dic 1998

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Adaptador de interfaz

LEADED-ADAPTER1 — Adaptador de montaje superficial a conector macho DIP para pruebas rápidas de encapsulados con plomo

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Guía del usuario: PDF
No disponible en TI.com
Modelo de simulación

SN74CBTLV3857 IBIS Model

SCDM053.ZIP (28 KB) - IBIS Model
Descargar
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (DW) 24 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Ver todos los temas del foro en inglés

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos