Información de empaque
| Encapsulado | Pines SOIC (DW) | 24 |
| Rango de temperatura de funcionamiento (℃) -40 to 85 |
| Cant. de paquetes | Empresa de transporte 2,000 | LARGE T&R |
Características para SN74CBTLV3857
- Enable Signal Is SSTL_2 Compatible
- Flow-Through Architecture Optimizes PCB Layout
- Designed for Use With 200 Mbit/s Double Data-Rate (DDR) SDRAM Applications
- Switch On-State Resistance Is Designed to Eliminate Series Resistor to DDR SDRAM
- Internal 10-k
Pulldown Resistors to Ground on B Port - Internal 50-k Pullup Resistor on Output-Enable Input
- Rail-to-Rail Switching on Data I/O Ports
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
Descripción de SN74CBTLV3857
This 10-bit FET bus switch is designed for 3-V to 3.6-V VCC operation and SSTL_2 output-enable (OE\) input levels.
When OE\ is low, the 10-bit bus switch is on, and port A is connected to port B. When OE\ is high, the switch is open, and
the high-impedance state exists between the two ports. There are 10-k pulldown resistors
to ground on the B port.
The FET switch on-state resistance is designed to replace the series terminating resistor in the SSTL_2 data path.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.