SN74HC139-Q1

Name: SN74HC139-Q1
Brand: TI
SKU: SN74HC139-Q1
Price: 0.124 USD

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Hoja de datos

document-pdfAcrobat Dual 2-Line to 4-Line Decoder/Demultiplexer datasheet (Rev. B) (Inglés)

SN74HC139-Q1

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Detalles del producto

Technology family

HC

Number of channels

2

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Supply current (max) (µA)

80

Technology family

HC

Number of channels

2

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Supply current (max) (µA)

80

SOIC (D)

16

59.4 mm² 9.9 x 6

TSSOP (PW)

16

32 mm² 5 x 6.4

Qualified for Automotive Applications
Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive up to Ten LSTTL Loads
Low Power Consumption, 80-µA Max I_CC
Typical t_pd = 10 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
ESD Protection Level per AEC-Q100 Classification
- 2000-V (H2) Human-Body Model
- 200-V (M3) Machine Model
- 1000-V (C5) Charged-Device Model

Qualified for Automotive Applications
Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive up to Ten LSTTL Loads
Low Power Consumption, 80-µA Max I_CC
Typical t_pd = 10 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
ESD Protection Level per AEC-Q100 Classification
- 2000-V (H2) Human-Body Model
- 200-V (M3) Machine Model
- 1000-V (C5) Charged-Device Model

The SN74HC139 device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The SN74HC139 device comprises two individual 2-line to 4-line decoders in a single package. The active-low enable G input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit.

The SN74HC139 device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The SN74HC139 device comprises two individual 2-line to 4-line decoders in a single package. The active-low enable G input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit.

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Documentación técnica

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	Tipo	Título	Fecha
*	Data sheet	Dual 2-Line to 4-Line Decoder/Demultiplexer datasheet (Rev. B)	24 abr 2008
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 jul 2021
	Selection guide	Logic Guide (Rev. AB)	12 jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 dic 2015
	More literature	Automotive Logic Devices Brochure	27 ago 2014
	User guide	LOGIC Pocket Data Book (Rev. B)	16 ene 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 jul 2004
	User guide	Signal Switch Data Book (Rev. A)	14 nov 2003
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 ago 2002
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 jun 1997
	Application note	Designing With Logic (Rev. C)	01 jun 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 oct 1996
	Application note	Live Insertion	01 oct 1996
	Application note	SN54/74HCT CMOS Logic Family Applications and Restrictions	01 may 1996
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc	01 abr 1996

Diseño y desarrollo

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Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

Guía del usuario: PDF | HTML

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Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
SOIC (D)	16	Ultra Librarian
TSSOP (PW)	16	Ultra Librarian

Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

SN74HC139-Q1

Decodificadores/Demultiplexores dobles de 2 a 4 líneas en catálogo automotriz

SN74HC139-Q1

Detalles del producto

Documentación técnica

Diseño y desarrollo

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

Pedidos y calidad

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