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Interruptores y multiplexores
Multiplexores y codificadores digitales

SN74LVC2G157

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Multiplexor/selector de datos únicos de 2 líneas a 1 línea

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SN74LVC2G157

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Detalles del producto

Technology family LVC Function Digital Multiplexer Configuration 2:1 Number of channels 4 Operating temperature range (°C) -40 to 85 Rating Catalog
Technology family LVC Function Digital Multiplexer Configuration 2:1 Number of channels 4 Operating temperature range (°C) -40 to 85 Rating Catalog
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Available in the Texas Instruments
    NanoFree™ package
  • Supports 5-V VCC operation
  • Inputs accept voltages to 5.5 V
  • Max tpd of 6 ns at 3.3 V
  • Low power consumption, 10-µA Maximum ICC
  • ±24-mA Output drive at 3.3 V
  • Typical VOLP (Output ground bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports live insertion, partial-power-down mode, and back-drive protection
  • Can be used as a down translator to translate inputs from a maximum of 5.5 V down
    to the VCC Level
  • Latch-up performance exceeds 100 mA per
    JESD 78, Class II
  • ESD Protection exceeds JESD 22
    • 2000-V Human body model (A114-A)
    • 1000-V Charged-device model (C101)
  • Available in the Texas Instruments
    NanoFree™ package
  • Supports 5-V VCC operation
  • Inputs accept voltages to 5.5 V
  • Max tpd of 6 ns at 3.3 V
  • Low power consumption, 10-µA Maximum ICC
  • ±24-mA Output drive at 3.3 V
  • Typical VOLP (Output ground bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports live insertion, partial-power-down mode, and back-drive protection
  • Can be used as a down translator to translate inputs from a maximum of 5.5 V down
    to the VCC Level
  • Latch-up performance exceeds 100 mA per
    JESD 78, Class II
  • ESD Protection exceeds JESD 22
    • 2000-V Human body model (A114-A)
    • 1000-V Charged-device model (C101)

This single 2-line to 1-line data selector multiplexer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G157 device features a common strobe (G) input. When the strobe is high, Y is low and Y is high. When the strobe is low, a single bit is selected from one of two sources and is routed to the outputs. The device provides true and complementary data.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This single 2-line to 1-line data selector multiplexer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G157 device features a common strobe (G) input. When the strobe is high, Y is low and Y is high. When the strobe is low, a single bit is selected from one of two sources and is routed to the outputs. The device provides true and complementary data.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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Documentación técnica

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* Data sheet SN74LVC2G157 Single 2-Line to 1-Line data selector multiplexer datasheet (Rev. N) PDF | HTML 04 mar 2019
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 jul 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note How to Select Little Logic (Rev. A) 26 jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 dic 2002
Application note Texas Instruments Little Logic Application Report 01 nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 may 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 dic 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note LVC Characterization Information 01 dic 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
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Modelo de simulación

HSPICE MODEL OF SN74LVC2G157

SCEJ234.ZIP (91 KB) - HSpice Model
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Modelo de simulación

SN74LVC2G157 IBIS Model (Rev. A)

SCEM298A.ZIP (44 KB) - IBIS Model
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
DSBGA (YZP) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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