CD74HC138-Q1

Name: CD74HC138-Q1
Brand: TI
SKU: CD74HC138-Q1
Price: 0.181 USD

활성

오토모티브 카탈로그 고속 CMOS 로직 3-8라인 디코더 디멀티플렉서 및 비인버팅

지금 주문

데이터 시트

document-pdfAcrobat High-Speed CMOS Logic 3- to 8-Line Inverting Decoder/Demultiplexer datasheet (Rev. A) (영어)

CD74HC138-Q1

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

HC

Number of channels

1

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Supply current (max) (µA)

160

Technology family

HC

Number of channels

1

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Supply current (max) (µA)

160

SOIC (D)

16

59.4 mm² 9.9 x 6

Qualified for Automotive Applications
Select One of Eight Data Outputs Active Low
I/O Port or Memory Selector
Three Enable Inputs to Simplify Cascading
Typical Propagation Delay of 13 ns at V_CC = 5 V, C_L = 15 pF, T_A = 25°C
Fanout (Over Temperature Range)
- Standard Outputs . . . 10 LSTTL Loads
- Bus Driver Outputs . . . 15 LSTTL Loads
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
2-V to 6-V V_CC Operation
High Noise Immunity; N_IL or N_IH = 30% of V_CC, V_CC = 5 V

Qualified for Automotive Applications
Select One of Eight Data Outputs Active Low
I/O Port or Memory Selector
Three Enable Inputs to Simplify Cascading
Typical Propagation Delay of 13 ns at V_CC = 5 V, C_L = 15 pF, T_A = 25°C
Fanout (Over Temperature Range)
- Standard Outputs . . . 10 LSTTL Loads
- Bus Driver Outputs . . . 15 LSTTL Loads
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
2-V to 6-V V_CC Operation
High Noise Immunity; N_IL or N_IH = 30% of V_CC, V_CC = 5 V

The CD74HC138 is a high-speed silicon-gate CMOS decoder well suited to memory address decoding or data routing applications. This circuit features low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low-power Schottky TTL logic. The circuit has three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine which one of the eight normally high outputs of the HC138 will go low.

Two active-low and one active-high enables (E1, E2, and E3) are provided to ease the cascading of decoders. The decoder’s eight outputs can drive ten low-power Schottky TTL equivalent loads.

The CD74HC138 is a high-speed silicon-gate CMOS decoder well suited to memory address decoding or data routing applications. This circuit features low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low-power Schottky TTL logic. The circuit has three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine which one of the eight normally high outputs of the HC138 will go low.

Two active-low and one active-high enables (E1, E2, and E3) are provided to ease the cascading of decoders. The decoder’s eight outputs can drive ten low-power Schottky TTL equivalent loads.

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