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신규 TAD5142 활성 Hardware-control stereo audio DAC with 110dB dynamic range, and headphone and line driver 6-dB higher performance with integrated headphone amplifier, HW controlled, QFN package

제품 상세 정보

Number of DAC channels 2 Analog inputs 0 Analog outputs 2 DAC SNR (typ) (dB) 100 Sampling rate (max) (kHz) 384 Control interface H/W Resolution (bps) 32 Architecture Delta Sigma with line driver Operating temperature range (°C) -25 to 85 Rating Catalog
Number of DAC channels 2 Analog inputs 0 Analog outputs 2 DAC SNR (typ) (dB) 100 Sampling rate (max) (kHz) 384 Control interface H/W Resolution (bps) 32 Architecture Delta Sigma with line driver Operating temperature range (°C) -25 to 85 Rating Catalog
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Ultra Low Out-of-Band Noise
  • Integrated High-Performance Audio PLL with BCK
    Reference to Generate SCK Internally
  • Direct Line Level 2.1-VRMS Output
  • No DC Blocking Capacitors Required
  • Line Level Output Down to 1KΩ
  • Intelligent Muting System; Soft Up or Down Ramp
    and Analog Mute For 120-dB Mute SNR
  • Accepts 16-, 24-, and 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified
  • Automatic Power-Save Mode When LRCK And
    BCK Are Deactivated
  • 1.8 V or 3.3 V Failsafe LVCMOS Digital Inputs
  • Simple Configuration Using Hardware Pins
  • Single-Supply Operation: 14
    • 3.3 V Analog, 1.8 V or 3.3 V Digital
  • Qualified in Accordance with AEC-Q100
  • Ultra Low Out-of-Band Noise
  • Integrated High-Performance Audio PLL with BCK
    Reference to Generate SCK Internally
  • Direct Line Level 2.1-VRMS Output
  • No DC Blocking Capacitors Required
  • Line Level Output Down to 1KΩ
  • Intelligent Muting System; Soft Up or Down Ramp
    and Analog Mute For 120-dB Mute SNR
  • Accepts 16-, 24-, and 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified
  • Automatic Power-Save Mode When LRCK And
    BCK Are Deactivated
  • 1.8 V or 3.3 V Failsafe LVCMOS Digital Inputs
  • Simple Configuration Using Hardware Pins
  • Single-Supply Operation: 14
    • 3.3 V Analog, 1.8 V or 3.3 V Digital
  • Qualified in Accordance with AEC-Q100

The PCM510xA devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.

The integrated line driver surpasses all other charge-pump based line drivers by supporting loads down to 1 kΩ per pin.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.

Intelligent clock error and PowerSense undervoltage protection utilizes a two-level mute system for pop-free performance.

Compared with many conventional switched capacitor DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured from the traditional 100-kHz OBN measurements to 3 MHz).

The PCM510xA devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.

The integrated line driver surpasses all other charge-pump based line drivers by supporting loads down to 1 kΩ per pin.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.

Intelligent clock error and PowerSense undervoltage protection utilizes a two-level mute system for pop-free performance.

Compared with many conventional switched capacitor DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured from the traditional 100-kHz OBN measurements to 3 MHz).

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기술 자료

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3개 모두 보기
유형 직함 날짜
* Data sheet PCM510xA 2.1 VRMS, 112/106/100 dB Audio Stereo DAC with PLL and 32-bit, 384 kHz PCM Interface datasheet (Rev. C) PDF | HTML 2015/05/06
EVM User's guide PCM510xEVM-U User Guide (Rev. C) 2014/10/13
Application note A Low Noise, Low Distortion Design for Antialiasing and Anti-Imaging Filters 2000/09/27

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

PCM5102EVM-U — PCM5102 평가 모듈

The PCM5102EVM-U is a complete evaluation kit for use with a personal computer running the Microsoft Windows™ operating system. The necessary evaluation software can be found online at the PCM5102 Product Folder.

The PCM5102EVM is in the Texas Instruments (TI) EVM form factor, which allows direct (...)

사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
패키지 CAD 기호, 풋프린트 및 3D 모델
TSSOP (PW) 20 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

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콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

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