홈 로직 및 전압 변환 버퍼, 드라이버 및 트랜시버 비인버팅 버퍼 및 드라이버
홈
로직 및 전압 변환
버퍼, 드라이버 및 트랜시버
비인버팅 버퍼 및 드라이버

SN54LVTH16244A-SP

활성

버스 홀드, TTL 호환 CMOS 입력 및 3상 출력을 지원하는 우주 항공 16채널, 2.7V~3.6V 버퍼

지금 주문
데이터 시트

SN54LVTH16244A-SP

활성
데이터 시트 지금 주문

제품 상세 정보

Technology family LVT Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 48 Supply current (max) (µA) 5000 IOH (max) (mA) -25 Input type TTL-Compatible CMOS Output type 3-State Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Space Operating temperature range (°C) -55 to 125
Technology family LVT Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 48 Supply current (max) (µA) 5000 IOH (max) (mA) -25 Input type TTL-Compatible CMOS Output type 3-State Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Space Operating temperature range (°C) -55 to 125
CFP (WD) 48 153.4008 mm² 15.88 x 9.66
  • Members of the Texas Instruments Widebus Family
  • State-of-the-Art Advanced BiCMOS
    Technology (ABT) Design for 3.3-V
    Operation and Low Static-Power
    Dissipation
  • Support Mixed-Mode Signal Operation
    (5-V Input and Output Voltages With
    3.3-V VCC)
  • Support Unregulated Battery Operation
    Down to 2.7 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up 3-State Support Hot
    Insertion
  • Bus Hold on Data Inputs Eliminates the Need
    for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Members of the Texas Instruments Widebus Family
  • State-of-the-Art Advanced BiCMOS
    Technology (ABT) Design for 3.3-V
    Operation and Low Static-Power
    Dissipation
  • Support Mixed-Mode Signal Operation
    (5-V Input and Output Voltages With
    3.3-V VCC)
  • Support Unregulated Battery Operation
    Down to 2.7 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up 3-State Support Hot
    Insertion
  • Bus Hold on Data Inputs Eliminates the Need
    for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

The 'LVTH16244A devices are 16-bit buffers and line drivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical active-low output-enable (OE)  inputs.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The 'LVTH16244A devices are 16-bit buffers and line drivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical active-low output-enable (OE)  inputs.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
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기술 자료

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22개 모두 보기
유형 직함 날짜
* Data sheet 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS, SNx4LVTH16244A datasheet (Rev. U) 2013/10/11
* SMD SN54LVTH16244A-SP SMD 5962-96685 2016/07/08
Application brief DLA Approved Optimizations for QML Products (Rev. B) PDF | HTML 2024/10/23
Selection guide TI Space Products (Rev. J) 2024/02/12
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 2023/08/31
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 2022/11/17
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022/10/19
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
Selection guide Advanced Bus Interface Logic Selection Guide 2001/01/09
Application note LVT-to-LVTH Conversion 1998/12/08
Application note LVT Family Characteristics (Rev. A) 1998/03/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

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시뮬레이션 모델

SN54LVTH16244A-SP IBIS MODEL

SLYM084.ZIP (12 KB) - IBIS Model
다운로드
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
CFP (WD) 48 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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