SN74AUP1G240
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
- Available in the Texas Instruments NanoStar™ Package
- Low Static-Power Consumption
- ICC = 0.9 µA Maximum
- Low Dynamic-Power Consumption
- Cpd = 4.2 pF at 3.3 V Typical
- Low Input Capacitance
- CI = 1.5 pF Typical
- Low Noise – Overshoot and Undershoot
<10% of VCC - Input-Disable Feature Allows Floating Input Conditions
- Ioff Supports Partial Power-Down-Mode Operation
- Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input
- Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 4.7 ns Maximum at 3.3 V
- Suitable for Point-to-Point Applications
The AUP family is TIs premier solution to the industrys low power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family ).
This buffer/driver is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.
To assure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | SN74AUP1G240 Low-Power Single Inverter With 3-State Output datasheet (Rev. D) | PDF | HTML | 2017/10/12 |
Application brief | Understanding Schmitt Triggers (Rev. A) | PDF | HTML | 2019/05/22 | |
Selection guide | Little Logic Guide 2018 (Rev. G) | 2018/07/06 | ||
Application note | Designing and Manufacturing with TI's X2SON Packages | 2017/08/23 | ||
Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
Application note | How to Select Little Logic (Rev. A) | 2016/07/26 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
5-8-LOGIC-EVM — 5핀~8핀 DCK, DCT, DCU, DRL 및 DBV 패키지용 일반 논리 평가 모듈
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
DSBGA (YZP) | 5 | Ultra Librarian |
SOT-23 (DBV) | 5 | Ultra Librarian |
SOT-SC70 (DCK) | 5 | Ultra Librarian |
USON (DRY) | 6 | Ultra Librarian |
X2SON (DPW) | 5 | Ultra Librarian |
X2SON (DSF) | 6 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치