SN74CB3Q3253
- High-Bandwidth Data Path (Up to 500 MHz) (1)
- 5-V Tolerant I/Os With Device Powered Up or Powered Down
- Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4 Ω Typical)
- Rail-to-Rail Switching on Data I/O Ports
- 0- to 5-V Switching With 3.3-V VCC
- 0- to 3.3-V Switching With 2.5-V VCC
- Bidirectional Data Flow With Near-Zero Propagation Delay
- Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical)
- Fast Switching Frequency (fOE = 20 MHz Max)
- Data and Control Inputs Provide Undershoot Clamp Diodes
- Low Power Consumption (ICC = 0.6 mA Typical)
- VCC Operating Range From 2.3 V to 3.6 V
- Data I/Os Support 0- to 5-V Signal Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
- Control Inputs Can be Driven by TTL or 5-V and 3.3-V CMOS Outputs
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
- Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface Bus Isolation, Low-Distortion Signal Gating (1)
(1) For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report CBT-C, CB3T, and CB3Q Signal-Switch Families, (SCDA008).
The SN74CB3Q3253 device is a high-bandwidth FET bus switch using a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input and output (I/O) ports.
기술 자료
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
LEADED-ADAPTER1 — TI의 5, 8, 10, 16 및 24핀 리드 패키지의 빠른 테스트를 위한 DIP 헤더 어댑터에 대한 표면 실장
The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages. The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.
LEADLESS-ADAPTER1 — TI의 6, 8, 10, 12, 14, 16 및 20핀 리드 없는 패키지의 테스트를 위한 DIP 헤더 어댑터에 대한 표면 실장
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
SSOP (DBQ) | 16 | Ultra Librarian |
TSSOP (PW) | 16 | Ultra Librarian |
TVSOP (DGV) | 16 | Ultra Librarian |
VQFN (RGY) | 16 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.