제품 상세 정보

Configuration 1:1 SPST Number of channels 2 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog, I2C, UART Ron (typ) (Ω) 5 CON (typ) (pF) 4 ON-state leakage current (max) (µA) 20 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 85 Features Powered-off protection, Signal path translation Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
Configuration 1:1 SPST Number of channels 2 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog, I2C, UART Ron (typ) (Ω) 5 CON (typ) (pF) 4 ON-state leakage current (max) (µA) 20 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 85 Features Powered-off protection, Signal path translation Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation on All Data
    I/O Ports
    • 5-V Input Down to 3.3-V Output Level Shift
      With 3.3-V VCC
    • 5-V/3.3-V Input Down to 2.5-V Output Level Shift
      With 2.5-V VCC
  • 5-V Tolerant I/Os With Device Powered Up or
    Powered Down
  • Bidirectional Data Flow With Near-Zero
    Propagation Delay
  • Low ON-State Resistance (ron) Characteristics (ron =
    5 Ω Typical)
  • Low Input/Output Capacitance Minimizes Loading
    (Cio(OFF) = 4.5 pF Typical)
  • Data and Control Inputs Provide Undershoot
    Clamp Diodes
  • Low Power Consumption (ICC = 20 µA Maximum)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels (0.8
    V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V
    CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Digital Applications:
    • Level Translation
    • USB Interface
    • Bus Isolation
  • Ideal for Low-Power Portable Equipment
  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation on All Data
    I/O Ports
    • 5-V Input Down to 3.3-V Output Level Shift
      With 3.3-V VCC
    • 5-V/3.3-V Input Down to 2.5-V Output Level Shift
      With 2.5-V VCC
  • 5-V Tolerant I/Os With Device Powered Up or
    Powered Down
  • Bidirectional Data Flow With Near-Zero
    Propagation Delay
  • Low ON-State Resistance (ron) Characteristics (ron =
    5 Ω Typical)
  • Low Input/Output Capacitance Minimizes Loading
    (Cio(OFF) = 4.5 pF Typical)
  • Data and Control Inputs Provide Undershoot
    Clamp Diodes
  • Low Power Consumption (ICC = 20 µA Maximum)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels (0.8
    V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V
    CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Digital Applications:
    • Level Translation
    • USB Interface
    • Bus Isolation
  • Ideal for Low-Power Portable Equipment

The SN74CB3T3306 device is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3306 device supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels.

The SN74CB3T3306 device is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3306 device supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels.

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기술 자료

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14개 모두 보기
유형 직함 날짜
* Data sheet SN74CB3T3306 Dual FET Bus Switch 2.5-V/3.3-V Low-Voltage Bus Switch With 5-V Tolerant Level Shifter datasheet (Rev. C) PDF | HTML 2015/12/31
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022/06/02
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021/12/01
Application note CBT-C, CB3T, and CB3Q Signal-Switch Families (Rev. C) PDF | HTML 2021/11/19
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 2021/01/06
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
More literature Digital Bus Switch Selection Guide (Rev. A) 2004/11/10
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Bus FET Switch Solutions for Live Insertion Applications 2003/02/07

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

DIP-ADAPTER-EVM — DIP 어댑터 평가 모듈

소형 표면 실장 IC(집적 회로)와 쉽고 빠르며 경제적인 방식으로 인터페이싱하는 방법을 제공하는 DIP 어댑터 평가 모듈(DIP-ADAPTER-EVM)로 연산 증폭기 프로토타이핑 및 테스트 속도를 높이세요. 제품에 포함된 Samtec 터미널 스트립을 사용하여 지원되는 연산 증폭기를 연결하거나 기존 회로에 직접 연결할 수 있습니다.

DIP 어댑터 EVM 키트는 다음을 포함해 가장 널리 사용되는 6개의 업계 표준 패키지를 지원합니다.

  • D 및 U(SOIC-8)
  • PW(TSSOP-8)
  • DGK(MSOP-8, VSSOP-8)
  • (...)
사용 설명서: PDF
TI.com에서 구매 불가
인터페이스 어댑터

LEADED-ADAPTER1 — TI의 5, 8, 10, 16 및 24핀 리드 패키지의 빠른 테스트를 위한 DIP 헤더 어댑터에 대한 표면 실장

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

SN74CB3T3306 IBIS Model

SCDM015.ZIP (25 KB) - IBIS Model
패키지 CAD 기호, 풋프린트 및 3D 모델
SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

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