제품 상세 정보

Protocols DDR2 Configuration 4:1 Number of channels 11 Bandwidth (MHz) 400 Supply voltage (max) (V) 1.9 Supply voltage (min) (V) 1.7 Ron (typ) (mΩ) 10000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 1.9 Supply current (typ) (µA) 700 ESD HBM (typ) (kV) 2.5 Operating temperature range (°C) 0 to 85 ESD CDM (kV) 0.75 Input/output continuous current (max) (mA) 100 COFF (typ) (pF) 2.5 CON (typ) (pF) 4.6 OFF-state leakage current (max) (µA) 10 Propagation delay time (µs) 0.000297 Ron (max) (mΩ) 17000 RON flatness (typ) (Ω) 1.5 Turnoff time (disable) (max) (ns) 2.1 Turnon time (enable) (max) (ns) 2.1 VIH (min) (V) 1.1 VIL (max) (V) 0.66
Protocols DDR2 Configuration 4:1 Number of channels 11 Bandwidth (MHz) 400 Supply voltage (max) (V) 1.9 Supply voltage (min) (V) 1.7 Ron (typ) (mΩ) 10000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 1.9 Supply current (typ) (µA) 700 ESD HBM (typ) (kV) 2.5 Operating temperature range (°C) 0 to 85 ESD CDM (kV) 0.75 Input/output continuous current (max) (mA) 100 COFF (typ) (pF) 2.5 CON (typ) (pF) 4.6 OFF-state leakage current (max) (µA) 10 Propagation delay time (µs) 0.000297 Ron (max) (mΩ) 17000 RON flatness (typ) (Ω) 1.5 Turnoff time (disable) (max) (ns) 2.1 Turnon time (enable) (max) (ns) 2.1 VIH (min) (V) 1.1 VIL (max) (V) 0.66
NFBGA (ZST) 72 49 mm² 7 x 7
  • Supports SSTL_18 signaling levels
  • Suitable for DDR-II applications
  • D-port outputs are precharged by bias voltage (VBIAS)
  • Internal termination for control inputs
  • High bandwidth (400 MHz minimum)
  • Low and flat ON-state resistance (ron) characteristics, (ron = 17 Ω maximum)
  • Internal 400-Ω pulldown resistors
  • Low differential and rising or falling edge skew
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • Supports SSTL_18 signaling levels
  • Suitable for DDR-II applications
  • D-port outputs are precharged by bias voltage (VBIAS)
  • Internal termination for control inputs
  • High bandwidth (400 MHz minimum)
  • Low and flat ON-state resistance (ron) characteristics, (ron = 17 Ω maximum)
  • Internal 400-Ω pulldown resistors
  • Low differential and rising or falling edge skew
  • Latch-up performance exceeds 100 mA per JESD 78, Class II

The SN74CBTU4411 device is a high-bandwidth, SSTL_18 compatible FET multiplexer/demultiplexer with low ON-state resistance (ron). The device uses an internal charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ron. The low and flat ron allows for minimal propagation delay and supports rail-to-rail signaling on data input/output (I/O) ports. The device also features very low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Matched ron and I/O capacitance among channels results in extremely low differential and rising or falling edge skew. This allows the device to show optimal performance in DDR-II applications.

The SN74CBTU4411 device is a high-bandwidth, SSTL_18 compatible FET multiplexer/demultiplexer with low ON-state resistance (ron). The device uses an internal charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ron. The low and flat ron allows for minimal propagation delay and supports rail-to-rail signaling on data input/output (I/O) ports. The device also features very low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Matched ron and I/O capacitance among channels results in extremely low differential and rising or falling edge skew. This allows the device to show optimal performance in DDR-II applications.

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관심 가지실만한 유사 제품

open-in-new 대안 비교
다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능
SN74CB3Q16811 활성 사전 충전 출력을 지원하는 3.3V, 1:1(SPST), 24채널 FET 버스 스위치 Higher supply range and lower Ron

기술 자료

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25개 모두 보기
유형 직함 날짜
* Data sheet SN74CBTU4411 11-Bit 1-of-4 Multiplexer or Demultiplexer 1.8-V DDR-II Switch With Charge Pump and Precharged Outputs datasheet (Rev. C) PDF | HTML 2021/09/13
Application brief 1.8-V Logic for Multiplexers and Signal Switches (Rev. C) PDF | HTML 2022/07/26
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
More literature Digital Bus Switch Selection Guide (Rev. A) 2004/11/10
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide Signal Switch Data Book (Rev. A) 2003/11/14
More literature CBT RAID Application Clip 2003/06/12
Application note Bus FET Switch Solutions for Live Insertion Applications 2003/02/07
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Flexible Voltage-Level Translation With CBT Family Devices 1999/07/20
User guide CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) 1998/12/01
Application note 3.3-V to 2.5-V Translation with Texas Instruments Crossbar Technology (Rev. A) 1998/04/03
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note 5-V To 3.3-V Translation With the SN74CBTD3384 (Rev. B) 1997/03/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

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시뮬레이션 모델

HSPICE Model for SN74CBTU4411

SCDJ034.ZIP (101 KB) - HSpice Model
시뮬레이션 모델

SN74CBTU4411 IBIS Model

SCDM101.ZIP (75 KB) - IBIS Model
패키지 CAD 기호, 풋프린트 및 3D 모델
NFBGA (ZST) 72 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

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