SN74F543
- 3-State True Outputs
- Back-to-Back Registers for Storage
- Package Options Include Plastic Small-Outline and Shrink Small-Outline Packages and Standard Plastic 300-mil DIPs
The SN74F543 octal transceiver contains two sets of D-type latches
for temporary storage of data flowing in either direction. Separate
latch-enable (
or 
) and output enable (
or 
) inputs are provided for each register to permit
independent control in either direction of data flow. The A outputs
are characterized to sink 24 mA while the B outputs are characterized
to sink 64 mA.
The A-to-B enable (
)
input must be low in order to enter data from A or to output data
from B. Having low and low makes the A-to-B latches
transparent; a subsequent low-to-high transition of puts the A latches in the storage
mode. With and both low, the 3-state B outputs
are active and reflect the data present at the output of the A
latches. Data flow from B to A is similar, but requires using the
, , and inputs.
The SN74F543 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN74F543 is characterized for operation from 0°C to 70°C.
A-to-B data flow is shown; B-to-A flow control is the same
except that it uses ,
, and .
Output level before the indicated steady-state input conditions were established.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | Octal Registered Transceiver With 3-State Outputs datasheet (Rev. B) | 1993/10/01 | |
| Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002/08/29 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997/08/01 | ||
| Application note | Designing With Logic (Rev. C) | 1997/06/01 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996/10/01 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOIC (DW) | 24 | Ultra Librarian |
| SSOP (DB) | 24 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치