SN74HC138-Q1

Name: SN74HC138-Q1
Brand: TI
SKU: SN74HC138-Q1
Price: 0.14 USD

활성

오토모티브 카탈로그 3라인-8라인 디코더/디멀티플렉서

지금 주문

데이터 시트

document-pdfAcrobat 3-Line to 8-Line Decoder/Demultiplexer datasheet (Rev. A) (영어)

SN74HC138-Q1

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

HC

Number of channels

1

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Supply current (max) (µA)

80

Technology family

HC

Number of channels

1

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Supply current (max) (µA)

80

SOIC (D)

16

59.4 mm² 9.9 x 6

TSSOP (PW)

16

32 mm² 5 x 6.4

Qualified for Automotive Applications
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
2-V to 6-V V_CC Operation
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max I_CC
Typical t_pd = 15 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception

Qualified for Automotive Applications
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
2-V to 6-V V_CC Operation
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max I_CC
Typical t_pd = 15 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception

The SN74HC138 is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

The SN74HC138 is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

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15개 모두 보기

	유형	직함	날짜
*	Data sheet	3-Line to 8-Line Decoder/Demultiplexer datasheet (Rev. A)	2008/09/17
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	2021/07/26
	Selection guide	Logic Guide (Rev. AB)	2017/06/12
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	2015/12/02
	More literature	Automotive Logic Devices Brochure	2014/08/27
	User guide	LOGIC Pocket Data Book (Rev. B)	2007/01/16
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	2004/07/08
	User guide	Signal Switch Data Book (Rev. A)	2003/11/14
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	2002/08/29
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	1997/06/01
	Application note	Designing With Logic (Rev. C)	1997/06/01
	Application note	Input and Output Characteristics of Digital Integrated Circuits	1996/10/01
	Application note	Live Insertion	1996/10/01
	Application note	SN54/74HCT CMOS Logic Family Applications and Restrictions	1996/05/01
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc	1996/04/01

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평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

사용 설명서: PDF | HTML

TI.com에서 구매 불가

패키지	핀	CAD 기호, 풋프린트 및 3D 모델
SOIC (D)	16	Ultra Librarian
TSSOP (PW)	16	Ultra Librarian

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SN74HC138-Q1

오토모티브 카탈로그 3라인-8라인 디코더/디멀티플렉서

SN74HC138-Q1

제품 상세 정보

기술 자료

설계 및 개발

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

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