홈 마이크로컨트롤러(MCU) 및 프로세서 DSP(디지털 신호 프로세서)
홈
마이크로컨트롤러(MCU) 및 프로세서
DSP(디지털 신호 프로세서)

TMS320DM369

활성

DaVinci 디지털 미디어 프로세서

지금 주문
데이터 시트
정오표

TMS320DM369

활성
데이터 시트 지금 주문

제품 상세 정보

DSP type 0 Operating system Linux Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) -40 to 85
DSP type 0 Operating system Linux Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (ZCE) 338 169 mm² 13 x 13
  • High-Performance Digital Media System-on-Chip (DMSoC)
    • 432-MHz ARMARM926EJ-S Clock Rate
    • 4:2:2 (8- and 16-Bit) Interface
    • Capable of 1080 p 30 fps H.264 Video Processing
    • Pin Compatible With DM365, DM368, DMVA1, and DMVA2 Processors
    • Fully Software-Compatible With ARM9
    • Extended Temperature Available for 432-MHz Device
    • Supports TI Third-Generation Noise Filter
    • Supports SMART Codec Feature for Very Low Bitrate
  • ARM® ARM926EJ-S™ Core
    • Support for 32-Bit and 16-Bit
      (Thumb Mode) Instruction Sets
    • DSP Instruction Extensions and Single-Cycle MAC
    • ARM® Jazelle Technology
    • Embedded ICE-RT Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 8KB of Data Cache
    • 32KB of RAM
    • 16KB of ROM
    • Little Endian
  • Three Video Image Coprocessors
    (Noise Filtering, HDVICP, MJCP) Engines
    • Supports a Range of Encode and Decode Operations
    • H.264, MPEG-4, MPEG-2, MJPEG, JPEG, WMV9 (VC-1)
    • Noise Filtering Engine
  • Video Processing Subsystem
    • Front End Provides:
      • Hardware Face Detect Engine
      • Hardware IPIPE for Real-Time Image Processing
        • Resize Engine
          • Resize Images From 1/16x to 8x
          • Separate Horizontal and Vertical Control
          • Two Simultaneous Output Paths
      • IPIPE Interface (IPIPEIF)
      • Image Sensor Interface (ISIF) and CMOS Imager Interface
      • 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz
      • Glueless Interface to Common Video Decoders
      • BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8- and 16-Bit) Interface
      • Histogram Module
      • Lens Distortion Correction (LDC) Module
      • Hardware 3A Statistics Collection Module (H3A)
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Composite NTSC/PAL Video Encoder Output
      • 8- and 16-Bit YCC and Up to 24-Bit RGB888 Digital Output
      • 3 Digital-to-Analog Converters (DACs) for HD Analog Video Output
      • LCD Controller
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8- and 16-Bit) Interface
  • Analog-to-Digital Converter (ADC)
  • Power Management and Real-Time Clock Subsystem (PRTCSS)
    • Real-Time Clock (RTC)
  • 16-Bit Host Port Interface (HPI)
  • 10/100 Mbps Ethernet Media Access Controller (EMAC) - Digital Media
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • Key Scan
  • Voice Codec
  • External Memory Interfaces (EMIFs)
    • DDR2 and mDDR SDRAM 16-Bit-Wide EMIF With 256MB of Address Space (1.8-V I/O)
    • Asynchronous 16- and 8-Bit-Wide EMIF (AEMIF)
      • Flash Memory Interfaces
        • NAND (8- and 16-Bit-Wide Data)
        • 16MB of NOR Flash, SRAM
        • OneNAND (16-Bit-Wide Data)
  • Flash Card Interfaces
    • Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
    • SmartMedia/xD
  • Enhanced Direct Memory Access (EDMA) Controller (64 Independent Channels)
  • USB Port With Integrated 2.0 High-Speed PHY that Supports
    • USB 2.0 High-Speed Device
    • USB 2.0 High-Speed Host (Mini-Host, Supporting One External Device)
    • USB On The Go (HS-USB OTG)
  • Four 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watchdog Timer
  • Two UARTs (One Fast UART With RTS and CTS Flow Control)
  • Five Serial Port Interfaces (SPIs) Each With Two Chip Selects
  • One Master or Slave Inter-Integrated Circuit (I2C) Bus™
  • One Multichannel Buffered Serial Port (McBSP)
    • I2S
    • AC97 Audio Codec Interface
    • S/PDIF Through Software
    • Standard Voice Codec Interface (AIC12)
    • SPI Protocol (Master Mode Only)
    • Direct Interface to T1 (E1) Framers
    • Time Division Multiplexed (TDM) Mode
    • 128-Channel Mode
  • Four Pulse Width Modulator (PWM) Outputs
  • Four RTO (Real-Time Out) Outputs
  • Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Boot Modes
    • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI
    • AEMIF (NOR and OneNAND)
  • Configurable Power-Saving Modes
  • Crystal or External Clock Input (Typically 19.2, 24, 27, or 36 MHz)
  • Flexible PLL Clock Generators
  • Debug Interface Support
    • IEEE 1149.1 (JTAG) Boundary-Scan-Compatible
    • ETB (Embedded Trace Buffer) With 4KB of Trace Buffer Memory
    • Device Revision ID Readable by ARM
  • 338-Pin Ball Grid Array (BGA) Package
    (ZCE Suffix), 0.65-mm Ball Pitch
  • 65-nm Process Technology
  • 3.3-V and 1.8-V I/O, 1.35-V Internal

All trademarks are the property of their respective owners.

  • High-Performance Digital Media System-on-Chip (DMSoC)
    • 432-MHz ARMARM926EJ-S Clock Rate
    • 4:2:2 (8- and 16-Bit) Interface
    • Capable of 1080 p 30 fps H.264 Video Processing
    • Pin Compatible With DM365, DM368, DMVA1, and DMVA2 Processors
    • Fully Software-Compatible With ARM9
    • Extended Temperature Available for 432-MHz Device
    • Supports TI Third-Generation Noise Filter
    • Supports SMART Codec Feature for Very Low Bitrate
  • ARM® ARM926EJ-S™ Core
    • Support for 32-Bit and 16-Bit
      (Thumb Mode) Instruction Sets
    • DSP Instruction Extensions and Single-Cycle MAC
    • ARM® Jazelle Technology
    • Embedded ICE-RT Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 8KB of Data Cache
    • 32KB of RAM
    • 16KB of ROM
    • Little Endian
  • Three Video Image Coprocessors
    (Noise Filtering, HDVICP, MJCP) Engines
    • Supports a Range of Encode and Decode Operations
    • H.264, MPEG-4, MPEG-2, MJPEG, JPEG, WMV9 (VC-1)
    • Noise Filtering Engine
  • Video Processing Subsystem
    • Front End Provides:
      • Hardware Face Detect Engine
      • Hardware IPIPE for Real-Time Image Processing
        • Resize Engine
          • Resize Images From 1/16x to 8x
          • Separate Horizontal and Vertical Control
          • Two Simultaneous Output Paths
      • IPIPE Interface (IPIPEIF)
      • Image Sensor Interface (ISIF) and CMOS Imager Interface
      • 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz
      • Glueless Interface to Common Video Decoders
      • BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8- and 16-Bit) Interface
      • Histogram Module
      • Lens Distortion Correction (LDC) Module
      • Hardware 3A Statistics Collection Module (H3A)
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Composite NTSC/PAL Video Encoder Output
      • 8- and 16-Bit YCC and Up to 24-Bit RGB888 Digital Output
      • 3 Digital-to-Analog Converters (DACs) for HD Analog Video Output
      • LCD Controller
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8- and 16-Bit) Interface
  • Analog-to-Digital Converter (ADC)
  • Power Management and Real-Time Clock Subsystem (PRTCSS)
    • Real-Time Clock (RTC)
  • 16-Bit Host Port Interface (HPI)
  • 10/100 Mbps Ethernet Media Access Controller (EMAC) - Digital Media
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • Key Scan
  • Voice Codec
  • External Memory Interfaces (EMIFs)
    • DDR2 and mDDR SDRAM 16-Bit-Wide EMIF With 256MB of Address Space (1.8-V I/O)
    • Asynchronous 16- and 8-Bit-Wide EMIF (AEMIF)
      • Flash Memory Interfaces
        • NAND (8- and 16-Bit-Wide Data)
        • 16MB of NOR Flash, SRAM
        • OneNAND (16-Bit-Wide Data)
  • Flash Card Interfaces
    • Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
    • SmartMedia/xD
  • Enhanced Direct Memory Access (EDMA) Controller (64 Independent Channels)
  • USB Port With Integrated 2.0 High-Speed PHY that Supports
    • USB 2.0 High-Speed Device
    • USB 2.0 High-Speed Host (Mini-Host, Supporting One External Device)
    • USB On The Go (HS-USB OTG)
  • Four 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watchdog Timer
  • Two UARTs (One Fast UART With RTS and CTS Flow Control)
  • Five Serial Port Interfaces (SPIs) Each With Two Chip Selects
  • One Master or Slave Inter-Integrated Circuit (I2C) Bus™
  • One Multichannel Buffered Serial Port (McBSP)
    • I2S
    • AC97 Audio Codec Interface
    • S/PDIF Through Software
    • Standard Voice Codec Interface (AIC12)
    • SPI Protocol (Master Mode Only)
    • Direct Interface to T1 (E1) Framers
    • Time Division Multiplexed (TDM) Mode
    • 128-Channel Mode
  • Four Pulse Width Modulator (PWM) Outputs
  • Four RTO (Real-Time Out) Outputs
  • Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Boot Modes
    • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI
    • AEMIF (NOR and OneNAND)
  • Configurable Power-Saving Modes
  • Crystal or External Clock Input (Typically 19.2, 24, 27, or 36 MHz)
  • Flexible PLL Clock Generators
  • Debug Interface Support
    • IEEE 1149.1 (JTAG) Boundary-Scan-Compatible
    • ETB (Embedded Trace Buffer) With 4KB of Trace Buffer Memory
    • Device Revision ID Readable by ARM
  • 338-Pin Ball Grid Array (BGA) Package
    (ZCE Suffix), 0.65-mm Ball Pitch
  • 65-nm Process Technology
  • 3.3-V and 1.8-V I/O, 1.35-V Internal

All trademarks are the property of their respective owners.

Developers can now deliver crystal-clear multiformat video at up to 1080 p H.264 at 30 fps (encode and closed-looped decode) in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM369 DaVinci™ video processors from TI.

The DM369 device is uniquely capable of running TI’s third-generation noise filtering technology while achieving low-light HD H.264 720p30 video compression and is pin-to-pin compatible with the DM365 processors, using the same ARM ARM926EJ-S core running at 432 MHz. This ARM9-based DM369 device supports production-qualified H.264BP/MP/HP, MPEG-4, MPEG-2, MJPEG, and WMV9 (VC-1) codecs providing customers with the flexibility to select the correct video codec for their application. These codecs run on independent coprocessors (HDVICP and MJCP) offloading all compression needs from the main ARM core. This lets developers obtain optimal performance from the ARM for their applications, including their multichannel, multistream, and multiformat needs.

Video surveillance designers achieve greater compression efficiency to provide more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players, and more can take advantage of the low power consumption and can ensure interoperability and product scalability by taking advantage of the full suite of codecs supported on the DM369 device.

Along with multiformat HD video, the DM369 processor also features a suite of peripherals that reduces system cost and complexity, thus enabling a seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.656, BT1120. The DM369 device also offers a high level of integration with HD display support, including three built-in 10-bit HD analog video digital-to-analog converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, host port interface (HPI), analog-to-digital converter (ADC), and many more features that reduce overall system costs and save real estate on circuit boards, thus allowing for a

Developers can now deliver crystal-clear multiformat video at up to 1080 p H.264 at 30 fps (encode and closed-looped decode) in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM369 DaVinci™ video processors from TI.

The DM369 device is uniquely capable of running TI’s third-generation noise filtering technology while achieving low-light HD H.264 720p30 video compression and is pin-to-pin compatible with the DM365 processors, using the same ARM ARM926EJ-S core running at 432 MHz. This ARM9-based DM369 device supports production-qualified H.264BP/MP/HP, MPEG-4, MPEG-2, MJPEG, and WMV9 (VC-1) codecs providing customers with the flexibility to select the correct video codec for their application. These codecs run on independent coprocessors (HDVICP and MJCP) offloading all compression needs from the main ARM core. This lets developers obtain optimal performance from the ARM for their applications, including their multichannel, multistream, and multiformat needs.

Video surveillance designers achieve greater compression efficiency to provide more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players, and more can take advantage of the low power consumption and can ensure interoperability and product scalability by taking advantage of the full suite of codecs supported on the DM369 device.

Along with multiformat HD video, the DM369 processor also features a suite of peripherals that reduces system cost and complexity, thus enabling a seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.656, BT1120. The DM369 device also offers a high level of integration with HD display support, including three built-in 10-bit HD analog video digital-to-analog converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, host port interface (HPI), analog-to-digital converter (ADC), and many more features that reduce overall system costs and save real estate on circuit boards, thus allowing for a
filter 기타 DSP(디지털 신호 프로세서) 찾기
다운로드 스크립트와 함께 비디오 보기 동영상
타사를 통해 지원

이 제품은 TI에서 지속적으로 직접 설계 지원을 제공하지 않습니다. 설계 작업 중 지원을 받으려면 다음 타사 중 하나에 문의할 수 있습니다. D3 Engineering, elnfochips, Ittiam Systems, Path Partner Technology 또는 Z3 Technologies.

기술 자료

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31개 모두 보기
유형 직함 날짜
* Data sheet TMS320DM369 Digital Media System-on-Chip (DMSoC) datasheet (Rev. A) PDF | HTML 2016/07/12
* Errata TMS320DM369 DMSoC Silicon Errata (Silicon Revision 1.2) [Ext] 2016/06/30
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023/02/24
User guide TMS320DM36x Reference Design Kit Quick Start Guide 2013/04/03
Analog Design Journal Converting single-ended video to differential video in single-supply systems 2011/09/16
User guide TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem User's Guide (Rev. B) 2011/08/03
User guide TMS320DM36x DMSoC General-Purpose Input/Output User's Guide (Rev. C) 2011/01/19
User guide TMS320DM36x DMSoC Ethernet Media Access Controller (EMAC) User's Guide (Rev. B) 2010/12/23
User guide TMS320DM36x DMSoC Video Processing Front End User's Guide (Rev. C) 2010/11/12
User guide TMS320DM36x DMSoC Video Processing Back End User's Guide (Rev. C) 2010/08/26
User guide TMS320DM36x DMSoC Voice Codec User's Guide (Rev. B) 2010/07/30
User guide TMS320DM36x DMSoC Face Detection User's Guide (Rev. A) 2010/07/21
User guide TMS320DM36x DMSoC Asynchronous External Memory Interface User's Guide (Rev. C) 2010/04/23
User guide TMS320DM36x DMSoC Multimedia Card/Secure Digital Card Controller User's Guide (Rev. B) 2010/04/23
More literature TMS320DM3x DaVinci Video Processors 2010/04/11
User guide TMS320DM36x DMSoC Key Scan User's Guide (Rev. A) 2010/03/01
User guide TMS320DM36x DMSoC Serial Peripheral Interface User's Guide (Rev. B) 2010/03/01
User guide TMS320DM36x DMSoC Universal Host Port Interface User's Guide (Rev. A) 2009/08/09
User guide TMS320DM36x DMSoC ARM Subsystem Reference Guide (Rev. A) 2009/08/07
User guide TMS320DM36x DMSoC Inter-Integrated Circuit User's Guide (Rev. A) 2009/08/07
User guide TMS320DM36x DMSoC Multichannel Buffered Serial Port User's Guide (Rev. A) 2009/08/07
User guide TMS320DM36x DMSoC Universal Serial Bus User's Guide (Rev. A) 2009/08/07
Application note TMS320DM36x SoC Architecture and Throughput 2009/07/29
User guide TMS320DM36x DMSoC Analog to Digital Converter User's Guide 2009/03/03
User guide TMS320DM36x DMSoC DDR2/mDDR Memory Controller User's Guide 2009/03/03
User guide TMS320DM36x DMSoC Enhanced Direct Memory Access Controller User's Guide 2009/03/03
User guide TMS320DM36x DMSoC Pulse-Width Modulator User's Guide 2009/03/03
User guide TMS320DM36x DMSoC Real Time Out User's Guide 2009/03/03
User guide TMS320DM36x DMSoC Timer/Watchdog Timer User's Guide 2009/03/03
User guide TMS320DM36x DMSoC Universal Asynchronous Receiver/Transmitter User's Guide 2009/03/03
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 2008/07/17

설계 및 개발

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평가 보드

TMDXEVM368 — TMS320DM36x 평가 모듈

The TMS320DM36x Digital Video Evaluation Module (DVEVM) enables developers to start immediate evaluation of TI’s Digital Media (DMx) processors and begin building digital video applications such as IP security cameras, action cameras, drones, wearables, digital signage, video doorbells, and (...)

사용 설명서: PDF
TI.com에서 구매 불가
소프트웨어 개발 키트(SDK)

LINUXDVSDK-DM36X — DM365, DM368 디지털 미디어 프로세서용 DVSDK(Linux 디지털 비디오 소프트웨어 개발 키트)

The Linux™ Digital Video Software Development Kits (DVSDKs) enable DaVinci™ system integrators to quickly develop Linux-based multimedia applications that can be easily ported across different devices in the DaVinci platform. Each DVSDK combines a pre-tested set of operating system, application (...)
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소프트웨어 코덱

DM36XCODECS — 코덱 - DM36x 디바이스에 최적화(DM365 및 DM368)

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)
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NFBGA (ZCE) 338 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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