제품 상세 정보

Configuration 2:1 SPDT Number of channels 1 Power supply voltage - single (V) 5, 12, 16, 20, 36, 44 Power supply voltage - dual (V) +/-10, +/-15, +/-18, +/-22, +/-5 Protocols Analog Ron (typ) (Ω) 2.1 CON (typ) (pF) 150 ON-state leakage current (max) (µA) 0.029 Supply current (typ) (µA) 25 Bandwidth (MHz) 40 Operating temperature range (°C) -55 to 125 Features 1.8-V compatible control inputs, Break-before-make, Fail-safe logic Input/output continuous current (max) (mA) 330 Rating Catalog Drain supply voltage (max) (V) 44 Supply voltage (max) (V) 44 Negative rail supply voltage (max) (V) -22
Configuration 2:1 SPDT Number of channels 1 Power supply voltage - single (V) 5, 12, 16, 20, 36, 44 Power supply voltage - dual (V) +/-10, +/-15, +/-18, +/-22, +/-5 Protocols Analog Ron (typ) (Ω) 2.1 CON (typ) (pF) 150 ON-state leakage current (max) (µA) 0.029 Supply current (typ) (µA) 25 Bandwidth (MHz) 40 Operating temperature range (°C) -55 to 125 Features 1.8-V compatible control inputs, Break-before-make, Fail-safe logic Input/output continuous current (max) (mA) 330 Rating Catalog Drain supply voltage (max) (V) 44 Supply voltage (max) (V) 44 Negative rail supply voltage (max) (V) -22
VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Dual supply range: ±4.5 V to ±22 V
  • Single supply range: 4.5 V to 44 V
  • –55°C to +125°C operating temperature
  • Low on-resistance: 2.1 Ω
  • Low charge injection: -10 pC
  • High current support: 330 mA (maximum)
  • Latch-up immune
  • 1.8 V logic compatible
  • Integrated pull-up and pull-down resistor on logic pins
  • Fail-safe logic
  • Rail-to-rail operation
  • Bidirectional signal path
  • Break-before-make switching
  • Dual supply range: ±4.5 V to ±22 V
  • Single supply range: 4.5 V to 44 V
  • –55°C to +125°C operating temperature
  • Low on-resistance: 2.1 Ω
  • Low charge injection: -10 pC
  • High current support: 330 mA (maximum)
  • Latch-up immune
  • 1.8 V logic compatible
  • Integrated pull-up and pull-down resistor on logic pins
  • Fail-safe logic
  • Rail-to-rail operation
  • Bidirectional signal path
  • Break-before-make switching

The TMUX7219M is a complementary metal-oxide semiconductor (CMOS) switch with latch-up immunity in a single channel, 2:1 (SPDT) configuration. The device works with a single supply (4.5 V to 44 V), dual supplies (±4.5 V to ±22 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The TMUX7219M supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from VSS to VDD.

The TMUX7219M can be enabled or disabled by controlling the EN pin. When disabled, both signal path switches are off. When enabled, the SEL pin can be used to turn on signal path 1 (S1 to D) or signal path 2 (S2 to D). All logic control inputs support logic levels from 1.8 V to VDD, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage.

The TMUX72xx family provides latch-up immunity, preventing undesirable high current events between parasitic structures within the device typically caused by overvoltage events. A latch-up condition typically continues until the power supply rails are turned off and can lead to device failure. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments. Additionally, the TMUX7219M is rated for extended temperature use down to –55°C, making it ideal for harsh industrial and aerospace applications.

The TMUX7219M is a complementary metal-oxide semiconductor (CMOS) switch with latch-up immunity in a single channel, 2:1 (SPDT) configuration. The device works with a single supply (4.5 V to 44 V), dual supplies (±4.5 V to ±22 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The TMUX7219M supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from VSS to VDD.

The TMUX7219M can be enabled or disabled by controlling the EN pin. When disabled, both signal path switches are off. When enabled, the SEL pin can be used to turn on signal path 1 (S1 to D) or signal path 2 (S2 to D). All logic control inputs support logic levels from 1.8 V to VDD, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage.

The TMUX72xx family provides latch-up immunity, preventing undesirable high current events between parasitic structures within the device typically caused by overvoltage events. A latch-up condition typically continues until the power supply rails are turned off and can lead to device failure. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments. Additionally, the TMUX7219M is rated for extended temperature use down to –55°C, making it ideal for harsh industrial and aerospace applications.

다운로드 스크립트와 함께 비디오 보기 동영상

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
1개 모두 보기
유형 직함 날짜
* Data sheet TMUX7219M 44-V, Latch-Up Immune, Extended Temperature, 2:1 (SPDT) Precision Switch with 1.8-V Logic datasheet PDF | HTML 2022/05/09

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

DIP-ADAPTER-EVM — DIP 어댑터 평가 모듈

소형 표면 실장 IC(집적 회로)와 쉽고 빠르며 경제적인 방식으로 인터페이싱하는 방법을 제공하는 DIP 어댑터 평가 모듈(DIP-ADAPTER-EVM)로 연산 증폭기 프로토타이핑 및 테스트 속도를 높이세요. 제품에 포함된 Samtec 터미널 스트립을 사용하여 지원되는 연산 증폭기를 연결하거나 기존 회로에 직접 연결할 수 있습니다.

DIP 어댑터 EVM 키트는 다음을 포함해 가장 널리 사용되는 6개의 업계 표준 패키지를 지원합니다.

  • D 및 U(SOIC-8)
  • PW(TSSOP-8)
  • DGK(MSOP-8, VSSOP-8)
  • (...)
사용 설명서: PDF
TI.com에서 구매 불가
평가 보드

TMUX72XXDGKEVM — TMUX72xx DGK 패키지 평가 모듈

TMUX72XXDGKEVM은 TMUX7219DGK를 포함해 8핀 VSSOP(DGK) 패키지의 TMUX72xx 장치 평가를 지원합니다. 이 평가 모듈은 특히 DC 매개변수를 위한 TMUX72xx 장치의 빠른 프로토타이핑 및 테스트에 사용할 수 있습니다.

사용 설명서: PDF
TI.com에서 구매 불가
인터페이스 어댑터

LEADED-ADAPTER1 — TI의 5, 8, 10, 16 및 24핀 리드 패키지의 빠른 테스트를 위한 DIP 헤더 어댑터에 대한 표면 실장

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

TMUX7219 IBIS model (Rev. B) (Rev. B)

SCDM249B.ZIP (263 KB) - IBIS Model
시뮬레이션 모델

TMUX7219 PSpice Model

SCDM261.ZIP (113 KB) - PSpice Model
패키지 CAD 기호, 풋프린트 및 3D 모델
VSSOP (DGK) 8 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상