TMUX7436F
- Wide supply voltage range:
- Single supply: 8 V to 44 V
- Dual supply: ±5 V to ±22 V
- Integrated fault protection:
- Overvoltage protection, source to supplies or source to drain: ±85 V
- Overvoltage protection: ±60 V
- Powered-off protection: ±60 V
- Interrupt flags to indicate fault status
- Output open circuited during fault
- Latch-up immunity by device construction
- 6 kV human body model (HBM) ESD rating
- Low On-Resistance: 8.6 Ω typical
- Flat On-Resistance: 10 mΩ typical
- 1.8-V Logic capable
-
Failsafe logic: up to 44 V independent of supply
- Industry-standard TSSOP and smaller WQFN packages
The TMUX7436F is a complementary metal-oxide semiconductor (CMOS) analog multiplexer with latch-up immunity in a dual channel, 2:1 configuration. The device works well with dual supplies (±5 V to ±22 V), a single supply (8 V to 44 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The overvoltage protection is available in powered and powered-off conditions, making the TMUX7436F device suitable for applications where power supply sequencing cannot be precisely controlled.
The device blocks fault voltages up to +60 V or −60 V relative to ground in powered and powered-off conditions. When no power supplies are present, the switch channels remain in the OFF state regardless of switch input conditions, and any control signal present on the logic pins is ignored. If the signal path input voltage on any Sx pin exceeds the supply voltage (VDD or VSS) by a threshold voltage (VT), then the channel turns OFF and the Sx pin becomes high impedance. The drain pin (Dx) is either pulled to the fault supply voltage that was exceeded or left floating depending on the DR control logic. The TMUX7436F device provides two active-low interrupt flags (FF and SF) to provide details of the fault and help system diagnostics. The FF flag indicates if any of the source inputs are experiencing a fault condition, while the SF flag is used to decode which specific inputs are experiencing a fault condition.
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기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | TMUX7436F ±60 V Fault-Protected, Dual 2:1 MultiplexerWith Latch-Up Immunity and 1.8 V Logic datasheet (Rev. A) | PDF | HTML | 2022/11/18 |
Application brief | How to Protect a Multi-Channel RTD System using Fault Protected Multiplexers (Rev. A) | PDF | HTML | 2024/08/08 | |
Application note | Protecting and Maintaining Signal Integrity in PLC Systems (Rev. A) | PDF | HTML | 2024/07/22 |
설계 및 개발
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The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages. The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.
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패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
TSSOP (PW) | 16 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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