제품 상세 정보

Configuration 2:1 SPDT Number of channels 2 Power supply voltage - single (V) 12, 16, 20, 36, 44 Power supply voltage - dual (V) +/-10, +/-15, +/-18, +/-22, +/-5 Protocols Analog Ron (typ) (Ω) 8.3 CON (typ) (pF) 30 ON-state leakage current (max) (µA) 0.027 Supply current (typ) (µA) 26 Bandwidth (MHz) 220 Operating temperature range (°C) -40 to 125 Features 1.8-V compatible control inputs, Break-before-make, Fail-safe logic, Overvoltage protection, Powered-off protection Input/output continuous current (max) (mA) 126.5 Rating Catalog Drain supply voltage (max) (V) 44 Supply voltage (max) (V) 44 Negative rail supply voltage (max) (V) -22
Configuration 2:1 SPDT Number of channels 2 Power supply voltage - single (V) 12, 16, 20, 36, 44 Power supply voltage - dual (V) +/-10, +/-15, +/-18, +/-22, +/-5 Protocols Analog Ron (typ) (Ω) 8.3 CON (typ) (pF) 30 ON-state leakage current (max) (µA) 0.027 Supply current (typ) (µA) 26 Bandwidth (MHz) 220 Operating temperature range (°C) -40 to 125 Features 1.8-V compatible control inputs, Break-before-make, Fail-safe logic, Overvoltage protection, Powered-off protection Input/output continuous current (max) (mA) 126.5 Rating Catalog Drain supply voltage (max) (V) 44 Supply voltage (max) (V) 44 Negative rail supply voltage (max) (V) -22
TSSOP (PW) 16 32 mm² 5 x 6.4
  • Wide supply voltage range:
    • Single supply: 8 V to 44 V
    • Dual supply: ±5 V to ±22 V
  • Integrated fault protection:
    • Overvoltage protection, source to supplies or source to drain: ±85 V
    • Overvoltage protection: ±60 V
    • Powered-off protection: ±60 V
    • Interrupt flags to indicate fault status
    • Output open circuited during fault
  • Latch-up immunity by device construction
  • 6 kV human body model (HBM) ESD rating
  • Low On-Resistance: 8.6 Ω typical
  • Flat On-Resistance: 10 mΩ typical
  • 1.8-V Logic capable
  • Failsafe logic: up to 44 V independent of supply

  • Industry-standard TSSOP and smaller WQFN packages
  • Wide supply voltage range:
    • Single supply: 8 V to 44 V
    • Dual supply: ±5 V to ±22 V
  • Integrated fault protection:
    • Overvoltage protection, source to supplies or source to drain: ±85 V
    • Overvoltage protection: ±60 V
    • Powered-off protection: ±60 V
    • Interrupt flags to indicate fault status
    • Output open circuited during fault
  • Latch-up immunity by device construction
  • 6 kV human body model (HBM) ESD rating
  • Low On-Resistance: 8.6 Ω typical
  • Flat On-Resistance: 10 mΩ typical
  • 1.8-V Logic capable
  • Failsafe logic: up to 44 V independent of supply

  • Industry-standard TSSOP and smaller WQFN packages

The TMUX7436F is a complementary metal-oxide semiconductor (CMOS) analog multiplexer with latch-up immunity in a dual channel, 2:1 configuration. The device works well with dual supplies (±5 V to ±22 V), a single supply (8 V to 44 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5  V). The overvoltage protection is available in powered and powered-off conditions, making the TMUX7436F device suitable for applications where power supply sequencing cannot be precisely controlled.

The device blocks fault voltages up to +60 V or −60 V relative to ground in powered and powered-off conditions. When no power supplies are present, the switch channels remain in the OFF state regardless of switch input conditions, and any control signal present on the logic pins is ignored. If the signal path input voltage on any Sx pin exceeds the supply voltage (VDD or VSS) by a threshold voltage (VT), then the channel turns OFF and the Sx pin becomes high impedance. The drain pin (Dx) is either pulled to the fault supply voltage that was exceeded or left floating depending on the DR control logic. The TMUX7436F device provides two active-low interrupt flags (FF and SF) to provide details of the fault and help system diagnostics. The FF flag indicates if any of the source inputs are experiencing a fault condition, while the SF flag is used to decode which specific inputs are experiencing a fault condition.

The TMUX7436F is a complementary metal-oxide semiconductor (CMOS) analog multiplexer with latch-up immunity in a dual channel, 2:1 configuration. The device works well with dual supplies (±5 V to ±22 V), a single supply (8 V to 44 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5  V). The overvoltage protection is available in powered and powered-off conditions, making the TMUX7436F device suitable for applications where power supply sequencing cannot be precisely controlled.

The device blocks fault voltages up to +60 V or −60 V relative to ground in powered and powered-off conditions. When no power supplies are present, the switch channels remain in the OFF state regardless of switch input conditions, and any control signal present on the logic pins is ignored. If the signal path input voltage on any Sx pin exceeds the supply voltage (VDD or VSS) by a threshold voltage (VT), then the channel turns OFF and the Sx pin becomes high impedance. The drain pin (Dx) is either pulled to the fault supply voltage that was exceeded or left floating depending on the DR control logic. The TMUX7436F device provides two active-low interrupt flags (FF and SF) to provide details of the fault and help system diagnostics. The FF flag indicates if any of the source inputs are experiencing a fault condition, while the SF flag is used to decode which specific inputs are experiencing a fault condition.

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
TMUX6236 활성 래치 업 내성 및 1.8V 로직을 지원하는 36V, 저 RON, 2:1(SPDT) 2채널 정밀 스위치 Replacement without fault protection and 36V supply
TMUX7236 활성 래치 업 내성 및 1.8V 로직을 지원하는 44V, 저 RON, 2:1(SPDT) 2채널 정밀 스위치 Replacement without fault protection and 44V supply
다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능
TMUX1136 활성 3PA 온 상태 누설 전류, 5V, 2:1, 2채널 정밀 아날로그 스위치 Same functionality without fault protection and 5V supply

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
3개 모두 보기
유형 직함 날짜
* Data sheet TMUX7436F ±60 V Fault-Protected, Dual 2:1 MultiplexerWith Latch-Up Immunity and 1.8 V Logic datasheet (Rev. A) PDF | HTML 2022/11/18
Application brief How to Protect a Multi-Channel RTD System using Fault Protected Multiplexers (Rev. A) PDF | HTML 2024/08/08
Application note Protecting and Maintaining Signal Integrity in PLC Systems (Rev. A) PDF | HTML 2024/07/22

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

인터페이스 어댑터

LEADED-ADAPTER1 — TI의 5, 8, 10, 16 및 24핀 리드 패키지의 빠른 테스트를 위한 DIP 헤더 어댑터에 대한 표면 실장

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

사용 설명서: PDF
TI.com에서 구매 불가
인터페이스 어댑터

LEADLESS-ADAPTER1 — TI의 6, 8, 10, 12, 14, 16 및 20핀 리드 없는 패키지의 테스트를 위한 DIP 헤더 어댑터에 대한 표면 실장

The EVM-LEADLESS1 board allows for quick testing and bread boarding of TI's common leadless packages.  The board has footprints to convert TI's DRC, DTP, DQE, RBW, RGY, RSE, RSV, RSW RTE, RTJ, RUK , RUC, RUG, RUM,RUT and YZP surface mount packages to 100mil DIP headers.
사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

TMUX7436F IBIS Model

SCDM304.ZIP (34 KB) - IBIS Model
패키지 CAD 기호, 풋프린트 및 3D 모델
TSSOP (PW) 16 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

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