패키징 정보
| 패키지 | 핀 HTSSOP (DDV) | 44 |
| 작동 온도 범위(°C) -40 to 105 |
| 패키지 수량 | 캐리어 2,000 | LARGE T&R |
TPA3255-Q1의 주요 특징
- AEC-Q100 Qualified for Automotive Applications
- Temperature Grade 2: –40°C to +105°C, TA
- Differential Analog Inputs
- Total Output Power at 10% THD+N
- 315-W Stereo into 4 Ω in BTL Configuration
- 180-W Stereo into 8 Ω in BTL Configuration
- 600-W Mono into 2 Ω in PBTL Configuration
- Total Output Power at 1% THD+N
- 255-W Stereo into 4 Ω in BTL Configuration
- 150-W Stereo into 8 Ω in BTL Configuration
- 495-W Mono into 2 Ω in PBTL Configuration
- Advanced Integrated Feedback Design with High-speed
Gate Driver Error Correction
- Signal Bandwidth up to 100 kHz for High Frequency Content From HD Sources
- Ultra Low 0.006% THD+N at 1 W into 4 Ω and <0.01% THD+N to Clipping
- >65 dB PSRR (BTL, 1 kHz, No Input Signal)
- <85 µV (A-Weighted) Output Noise
- >111 dB (A Weighted) SNR
- Multiple Configurations Possible:
- Stereo, Mono, 2.1 and 4xSE
- Click and Pop Free Startup and Stop
- 90% Efficient Class-D Operation (4 Ω)
- Wide 18-V to 53.5V Supply Voltage Operation
- Self-Protection Design (Including Undervoltage, Overtemperature, Clipping, and Short Circuit Protection) With Error Reporting
TPA3255-Q1에 대한 설명
TPA3255-Q1 is a high performance class-D power amplifier that enables true premium sound quality with class-D efficiency. It features an advanced integrated feedback design and proprietary high-speed gate driver error correction (PurePath™ Ultra-HD). This technology allows ultra low distortion across the audio band and superior audio quality. The device is operated in AD-mode, and can drive up to 2 x 315 W into 4-Ω load at 10% THD and 2 x 150 W unclipped into 8-Ω load and features a 2-VRMS analog input interface that works seamlessly with high performance DACs such as TI’s PCM5242. In addition to excellent audio performance, TPA3255-Q1 achieves both high power efficiency and very low power stage idle losses below 2.5W. This is achieved through the use of 85-mΩ MOSFETs and an optimized gate driver scheme that achieves significantly lower idle losses than typical discrete implementations.