제품 상세 정보

Configuration 2:1 SPDT Number of channels 1 Power supply voltage - single (V) 2.5, 3.3, 5 Protocols Analog Ron (typ) (Ω) 0.5 CON (typ) (pF) 133 ON-state leakage current (max) (µA) 0.2 Supply current (typ) (µA) 0.01 Bandwidth (MHz) 43 Operating temperature range (°C) -40 to 85 Features 1.8-V compatible control inputs, Break-before-make Input/output continuous current (max) (mA) 450 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
Configuration 2:1 SPDT Number of channels 1 Power supply voltage - single (V) 2.5, 3.3, 5 Protocols Analog Ron (typ) (Ω) 0.5 CON (typ) (pF) 133 ON-state leakage current (max) (µA) 0.2 Supply current (typ) (µA) 0.01 Bandwidth (MHz) 43 Operating temperature range (°C) -40 to 85 Features 1.8-V compatible control inputs, Break-before-make Input/output continuous current (max) (mA) 450 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25
  • Specified Break-Before-Make Switching
  • Low ON-State Resistance (0.75 Max)
  • Control Inputs Referenced to VIO
  • Low Charge Injection
  • Excellent ON-State Resistance Matching
  • Low Total Harmonic Distortion (THD)
  • 2.25-V to 5.5-V Power Supply (V+)
  • 1.65-V to 1.95-V Logic Supply (VIO)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 4000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
    • 400-V Machine Model (A115-A)
  • COM Port to GND
    • 8000-V Human-Body Model
      (A114-B, Class II)
    • ±15-kV Contact Discharge (IEC 61000-4-2)
  • APPLICATIONS
    • Cell Phones
    • PDAs
    • Portable Instrumentation

  • Specified Break-Before-Make Switching
  • Low ON-State Resistance (0.75 Max)
  • Control Inputs Referenced to VIO
  • Low Charge Injection
  • Excellent ON-State Resistance Matching
  • Low Total Harmonic Distortion (THD)
  • 2.25-V to 5.5-V Power Supply (V+)
  • 1.65-V to 1.95-V Logic Supply (VIO)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 4000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
    • 400-V Machine Model (A115-A)
  • COM Port to GND
    • 8000-V Human-Body Model
      (A114-B, Class II)
    • ±15-kV Contact Discharge (IEC 61000-4-2)
  • APPLICATIONS
    • Cell Phones
    • PDAs
    • Portable Instrumentation

The TS5A6542 is a single-pole double-throw (SPDT) analog switch that is designed to operate from 2.25 V to 5.5 V. The device offers a low ON-state resistance with an excellent channel-to-channel ON-state resistance matching, and the break-before-make feature to prevent signal distorion during the transferring of a signal from one path to another. The device has excellent total harmonic distortion (THD) performance and consumes very low power. These features make this device suitable for portable audio applications.

The TS5A6542 has a separate logic supply pin (VIO) that is characterized to operate from 1.65 V to 1.95 V. VIO powers the control circuitry, which allows the TS5A6542 to be controlled by 1.8-V signals.

The TS5A6542 is a single-pole double-throw (SPDT) analog switch that is designed to operate from 2.25 V to 5.5 V. The device offers a low ON-state resistance with an excellent channel-to-channel ON-state resistance matching, and the break-before-make feature to prevent signal distorion during the transferring of a signal from one path to another. The device has excellent total harmonic distortion (THD) performance and consumes very low power. These features make this device suitable for portable audio applications.

The TS5A6542 has a separate logic supply pin (VIO) that is characterized to operate from 1.65 V to 1.95 V. VIO powers the control circuitry, which allows the TS5A6542 to be controlled by 1.8-V signals.

다운로드 스크립트와 함께 비디오 보기 동영상

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
6개 모두 보기
유형 직함 날짜
* Data sheet TS5A6542 0.75-Ohm SPDT Analog Switch With Input Logic Translation datasheet (Rev. C) 2009/12/11
Application note High-Efficiency Charging for TWS Using a 2-Pin Interface Application Report (Rev. A) PDF | HTML 2023/05/16
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022/06/02
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021/12/01
Application note Preventing Excess Power Consumption on Analog Switches 2008/07/03
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

인터페이스 어댑터

LEADLESS-ADAPTER1 — TI의 6, 8, 10, 12, 14, 16 및 20핀 리드 없는 패키지의 테스트를 위한 DIP 헤더 어댑터에 대한 표면 실장

The EVM-LEADLESS1 board allows for quick testing and bread boarding of TI's common leadless packages.  The board has footprints to convert TI's DRC, DTP, DQE, RBW, RGY, RSE, RSV, RSW RTE, RTJ, RUK , RUC, RUG, RUM,RUT and YZP surface mount packages to 100mil DIP headers.
사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

HSPICE MODEL OF TS5A6542

SCEJ226.ZIP (90 KB) - HSpice Model
시뮬레이션 모델

TS5A6542 IBIS Model

SCEM514.ZIP (67 KB) - IBIS Model
패키지 CAD 기호, 풋프린트 및 3D 모델
DSBGA (YZP) 8 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상