TS5A6542
- Specified Break-Before-Make Switching
- Low ON-State Resistance (0.75 Max)
- Control Inputs Referenced to VIO
- Low Charge Injection
- Excellent ON-State Resistance Matching
- Low Total Harmonic Distortion (THD)
- 2.25-V to 5.5-V Power Supply (V+)
- 1.65-V to 1.95-V Logic Supply (VIO)
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 4000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 400-V Machine Model (A115-A)
- 4000-V Human-Body Model
- COM Port to GND
- 8000-V Human-Body Model
(A114-B, Class II) - ±15-kV Contact Discharge (IEC 61000-4-2)
- 8000-V Human-Body Model
- APPLICATIONS
- Cell Phones
- PDAs
- Portable Instrumentation
The TS5A6542 is a single-pole double-throw (SPDT) analog switch that is designed to operate from 2.25 V to 5.5 V. The device offers a low ON-state resistance with an excellent channel-to-channel ON-state resistance matching, and the break-before-make feature to prevent signal distorion during the transferring of a signal from one path to another. The device has excellent total harmonic distortion (THD) performance and consumes very low power. These features make this device suitable for portable audio applications.
The TS5A6542 has a separate logic supply pin (VIO) that is characterized to operate from 1.65 V to 1.95 V. VIO powers the control circuitry, which allows the TS5A6542 to be controlled by 1.8-V signals.
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | TS5A6542 0.75-Ohm SPDT Analog Switch With Input Logic Translation datasheet (Rev. C) | 2009/12/11 | |
Application note | High-Efficiency Charging for TWS Using a 2-Pin Interface Application Report (Rev. A) | PDF | HTML | 2023/05/16 | |
Application note | Selecting the Correct Texas Instruments Signal Switch (Rev. E) | PDF | HTML | 2022/06/02 | |
Application note | Multiplexers and Signal Switches Glossary (Rev. B) | PDF | HTML | 2021/12/01 | |
Application note | Preventing Excess Power Consumption on Analog Switches | 2008/07/03 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 |
설계 및 개발
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패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
DSBGA (YZP) | 8 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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