首頁 數據轉換器 類比轉數位轉換器 (ADC) 高速 ADC (≥10 MSPS)
首頁
數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC12DL3200

現行

12 位元、雙 3.2-GSPS 或單 6.4-GSPS、射頻取樣類比轉數位轉換器 (LVDS 介面)

立即訂購
產品規格表

ADC12DL3200

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 3200, 6400 Resolution (bps) 12 Number of input channels 1, 2 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3150 Architecture Folding Interpolating SNR (dB) 57.9 ENOB (bit) 9 SFDR (dB) 78 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 3200, 6400 Resolution (bps) 12 Number of input channels 1, 2 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3150 Architecture Folding Interpolating SNR (dB) 57.9 ENOB (bit) 9 SFDR (dB) 78 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCBGA (ACF) 256 289 mm² 17 x 17 FCBGA (ALJ) 256 289 mm² 17 x 17
  • ADC Core:
    • 12-Bit Resolution
    • Up to 6.4 GSPS in Single-Channel Mode
    • Up to 3.2 GSPS in Dual-Channel Mode
  • Internal Dither for Low-Magnitude, High-Order Harmonics
  • Low-Latency LVDS Interface:
    • Total Latency: < 10 ns
    • Up to 48 Data Pairs at 1.6 Gbps
    • Four DDR Data Clocks
    • Strobe Signals Simplify Synchronization
  • Noise Floor (No Input, V FS = 1.0 V PP-DIFF):
    • Dual-Channel Mode: –151.1 dBFS/Hz
    • Single-Channel Mode: –154.3 dBFS/Hz
  • Buffered Analog Inputs With V CMI of 0 V:
    • Analog Input Bandwidth (–3 dB): 8.0 GHz
    • Usable Input Frequency Range: > 10 GHz
    • Full-Scale Input Voltage (V FS, Default): 0.8 V PP
  • Noiseless Aperture Delay (T AD) Adjustment:
    • Precise Sampling Control: 19-fs Step
    • Simplifies Synchronization and Interleaving
    • Temperature and Voltage Invariant Delays
  • Easy-to-Use Synchronization Features:
    • Automatic SYSREF Timing Calibration
    • Timestamp for Sample Marking
  • Power Consumption: 3.15 W
  • ADC Core:
    • 12-Bit Resolution
    • Up to 6.4 GSPS in Single-Channel Mode
    • Up to 3.2 GSPS in Dual-Channel Mode
  • Internal Dither for Low-Magnitude, High-Order Harmonics
  • Low-Latency LVDS Interface:
    • Total Latency: < 10 ns
    • Up to 48 Data Pairs at 1.6 Gbps
    • Four DDR Data Clocks
    • Strobe Signals Simplify Synchronization
  • Noise Floor (No Input, V FS = 1.0 V PP-DIFF):
    • Dual-Channel Mode: –151.1 dBFS/Hz
    • Single-Channel Mode: –154.3 dBFS/Hz
  • Buffered Analog Inputs With V CMI of 0 V:
    • Analog Input Bandwidth (–3 dB): 8.0 GHz
    • Usable Input Frequency Range: > 10 GHz
    • Full-Scale Input Voltage (V FS, Default): 0.8 V PP
  • Noiseless Aperture Delay (T AD) Adjustment:
    • Precise Sampling Control: 19-fs Step
    • Simplifies Synchronization and Interleaving
    • Temperature and Voltage Invariant Delays
  • Easy-to-Use Synchronization Features:
    • Automatic SYSREF Timing Calibration
    • Timestamp for Sample Marking
  • Power Consumption: 3.15 W

The ADC12DL3200 is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DL3200 can sample up to 3200 MSPS and in single-channel mode up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz and a useable frequency range allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DL3200 uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6 Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (T AD) adjustment and SYSREF windowing.

The ADC12DL3200 is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DL3200 can sample up to 3200 MSPS and in single-channel mode up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz and a useable frequency range allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DL3200 uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6 Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (T AD) adjustment and SYSREF windowing.
filter 尋找其它 高速 ADC (≥10 MSPS)
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 3
類型 標題 日期
* Data sheet ADC12DL3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 12-Bit Analog-to-Digital Converter (ADC) With LVDS Interface datasheet (Rev. C) PDF | HTML 2023年 5月 23日
EVM User's guide ADC12DLXX00 Evaluation Module User's Guide (Rev. A) PDF | HTML 2023年 12月 7日
EVM User's guide TSW14DL3200EVM High-Speed LVDS Data Capture and Pattern Generator User's Guide 2018年 5月 15日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

ADC12DL3200EVM — ADC12DL3200 12 位元雙路 3.2 GSPS 或單路 6.4 GSPS 射頻取樣 ADC 評估模組

ADC12DL3200 評估模組 (EVM) 用於評估 ADC12DL3200，是一款具有 LVDS 介面的 12 位元、雙 3.2-GSPS 或單 6.4-GSPS、射頻取樣類比轉數位轉換器 (ADC)。EVM 具備單端 AC 耦合類比輸入、板載 ADC 時鐘產生及電源調節電路。ADC12DL3200EVM 設計為直接連接 TSW14JDL3200EVM。

透過高速資料轉換器專業級軟體 (DATACONVERTERPRO-SW) 分析工具提供額外支援。

使用指南: PDF | HTML
TI.com 無法提供
韌體

SLVC814 — TSW14DL3200 ADC12DL3200 Reference Design Firmware

支援產品和硬體

支援產品和硬體

產品
高速 ADC (≥10 MSPS)
ADC12DL3200 — 12 位元、雙 3.2-GSPS 或單 6.4-GSPS、射頻取樣類比轉數位轉換器 (LVDS 介面)
硬體開發
開發板
TSW14DL3200EVM — 數據擷取/模式產生器：具有 48 個最高達 1.6Gbps 之 LVDS 通道的數據轉換器評估模組
下載
開發模組 (EVM) 的 GUI

SLVC719 — ADC12DLxx00EVM GUI

支援產品和硬體

支援產品和硬體

產品
高速 ADC (≥10 MSPS)
ADC12DL3200 — 12 位元、雙 3.2-GSPS 或單 6.4-GSPS、射頻取樣類比轉數位轉換器 (LVDS 介面)
硬體開發
開發板
ADC12DL3200EVM — ADC12DL3200 12 位元雙路 3.2 GSPS 或單路 6.4 GSPS 射頻取樣 ADC 評估模組
下載
外掛程式

ABACO-3P-FMC172 — Abaco Systems ® 寬帶低延遲高速 ADC/DAC 模組夾層介面卡

The Abaco FMC172 module highlights the Texas Instruments low-latency ADC12DL3200 one-channel 6.4-GSPS analog-to-digital converter (ADC) in a daughtercard with an FPGA mezzanine card (FMC) connector. The combination of FMC172 >6-GHz bandwidth, high sample rate, and low latency is ideal (...)
從：Abaco Systems
造訪合作夥伴網站
模擬型號

ADC12DL3200 IBIS Model

SLVMCP2.ZIP (53 KB) - IBIS Model
下載
模擬型號

ADC12DL3200 IBIS Model (Rev. A)

SLVMCP2A.ZIP (68 KB) - IBIS Model
下載
Gerber 檔案

ADC12DL3200EVM Design File

SLVC726.ZIP (12398 KB)
下載
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (ACF) 256 Ultra Librarian
FCBGA (ALJ) 256 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片