產品詳細資料

Function General-purpose timer Iq (typ) (mA) 2 Rating Catalog Operating temperature range (°C) -40 to 105 Supply voltage (max) (V) 16 Supply voltage (min) (V) 4.5
Function General-purpose timer Iq (typ) (mA) 2 Rating Catalog Operating temperature range (°C) -40 to 105 Supply voltage (max) (V) 16 Supply voltage (min) (V) 4.5
PDIP (P) 8 92.5083 mm² 9.81 x 9.43 SOIC (D) 8 29.4 mm² 4.9 x 6
  • Timing From Microseconds to Hours
  • Astable or Monostable Operation
  • Adjustable Duty Cycle
  • TTL-Compatible Output Can Sink or Source
    Up to 200 mA
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include
    Testing of All Parameters.
  • Timing From Microseconds to Hours
  • Astable or Monostable Operation
  • Adjustable Duty Cycle
  • TTL-Compatible Output Can Sink or Source
    Up to 200 mA
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include
    Testing of All Parameters.

These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor.

The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.

The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.

These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor.

The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.

The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.

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類型 標題 日期
* Data sheet xx555 Precision Timers datasheet (Rev. I) PDF | HTML 2014年 9月 15日
Application note Considering TI Smart DACs As an Alternative to 555 Timers PDF | HTML 2021年 9月 2日
Design guide AC-Coupled RS-485 Design Guide 2016年 6月 15日
Design guide Automatic Direction Control RS-485 Design Guide 2016年 6月 2日

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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
參考設計

TIDA-01365 — 雙向 RS-485 扇出集線器參考設計

The Bidirectional RS-485 Fan-Out Hub Reference Design (TIDA-01365) documents and tests an RS-485 fan-out hub design where 1:N and N:1 RS-485 signals are aggregated in and out of any bus topology. This design also features automatic direction control, for reduced pin count on microcontrollers, and (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01090 — RS-485 自動方向控制參考設計

The TIDA-01090 reference design enables half-duplex communication over an RS-485 bus without requiring additional driver-enable/receiver-enable controls.  The design allows for the transceiver used on each node to go into transmit mode automatically when data is being transmitted from a local (...)
Design guide: PDF
電路圖: PDF
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PDIP (P) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian

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