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可編程與可變增益放大器 (PGA 與 VGA)

PGA117

現行

具 10 通道多工器的零漂移、100-µV 偏移、12-nV/√Hz 雜訊、RRO (範圍增益) 可編程增益放大器

立即訂購
產品規格表

PGA117

現行
產品規格表 立即訂購

產品詳細資料

Features Daisy chain, Scope gains, Shutdown PGA/VGA PGA Number of channels 10 Interface type SPI Vs (max) (V) 5.5 Vs (min) (V) 2.2 Input type Single-ended Vos (offset voltage at 25°C) (typ) (V) 0.000025 Input offset drift (±) (typ) (V/°C) 0.0000006 Input voltage noise (typ) (V√Hz) 0.000000012 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 3 Iq per channel (typ) (mA) 1.08 Gain (max) (dB) 46 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Architecture CMOS Operating temperature range (°C) -40 to 125 Noise at 1 kHz (typ) (V√Hz) 0.000000013 Output type Single-ended
Features Daisy chain, Scope gains, Shutdown PGA/VGA PGA Number of channels 10 Interface type SPI Vs (max) (V) 5.5 Vs (min) (V) 2.2 Input type Single-ended Vos (offset voltage at 25°C) (typ) (V) 0.000025 Input offset drift (±) (typ) (V/°C) 0.0000006 Input voltage noise (typ) (V√Hz) 0.000000012 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 3 Iq per channel (typ) (mA) 1.08 Gain (max) (dB) 46 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Architecture CMOS Operating temperature range (°C) -40 to 125 Noise at 1 kHz (typ) (V√Hz) 0.000000013 Output type Single-ended
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Rail-to-Rail Input and Output
  • Offset: 25 µV (Typical), 100 µV
    (Maximum)
  • Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 µA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI™ Interface (10 MHz) With Daisy-Chain
    Capability
  • Rail-to-Rail Input and Output
  • Offset: 25 µV (Typical), 100 µV
    (Maximum)
  • Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 µA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI™ Interface (10 MHz) With Daisy-Chain
    Capability

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.
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功能相同，但引腳輸出與所比較的裝置不同
PGA112 現行 具 2 通道多工器的零漂移、100-µV 偏移、12-nV/√Hz 雜訊、RRO (二進位增益) 可編程增益放大器 This device offers 2 channel mux instead of 10 channel mux, and binary gains instead of scope gains.
PGA113 現行 具 2 通道多工器的零漂移、100-µV 偏移、12-nV/√Hz 雜訊、RRO (範圍增益) 可編程增益放大器 This device offers 2 channel mux instead of 10 channel mux,

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* Data sheet PGA11x Zerø-Drift Programmable Gain Amplifier With Mux datasheet (Rev. C) PDF | HTML 2015年 11月 30日

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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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參考設計

TIDA-00130 — 適用於斷路器 (ACB/MCCB-ETU) 的零飄移 PGA 架構類比前端設計

This reference design is intended for use in molded case circuit breakers (MCCB) electronic trip units.  The programmable gain amplifier based design acts as the current monitoring for over-current earth fault relays. Utilizing a zero drift programmable amplifier, this design provides a (...)
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