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微控制器 (MCU) 與處理器
Arm 式處理器

TDA4AL-Q1

現行

使用攝影機和雷達感測器，且適用前攝影機與 ADAS 網域控制的車用系統單晶片

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TDA4AL-Q1

現行
產品規格表 立即訂購

產品詳細資料

Arm CPU 2 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors 2 Arm Cortex-R5F, MCU Island of 2 Arm Cortex-R5F (lockstep opt) CPU 64-bit Display type 1 DSI, MIPI DPI Ethernet MAC 2-Port 10/100/1000 Hardware accelerators 1 deep learning accelerator, 1 depth and motion accelerator, 1 video encode accelerator, 1 vision pre-processing accelerator Features Vision Analytics Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment Rating Automotive Power supply solution LP8764-Q1, TPS6594-Q1 Operating temperature range (°C) -40 to 125
Arm CPU 2 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors 2 Arm Cortex-R5F, MCU Island of 2 Arm Cortex-R5F (lockstep opt) CPU 64-bit Display type 1 DSI, MIPI DPI Ethernet MAC 2-Port 10/100/1000 Hardware accelerators 1 deep learning accelerator, 1 depth and motion accelerator, 1 video encode accelerator, 1 vision pre-processing accelerator Features Vision Analytics Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment Rating Automotive Power supply solution LP8764-Q1, TPS6594-Q1 Operating temperature range (°C) -40 to 125
FCBGA (ALZ) 770 529 mm² 23 x 23

Processor cores:

  • Two C7x floating point, vector DSP, up to 1.0GHz, 160GFLOPS, 512GOPS
  • Deep-learning matrix multiply accelerator (MMA), up to 8TOPS (8b) at 1.0GHz
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2GHz
    • 1MB shared L2 cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Up to Six Arm Cortex-R5F MCUs at up to 1.0GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Four (TDA4VE) or Two (TDA4AL/TDA4VL) Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800MHz, 50GFLOPS, 4GTexels/s (TDA4VE and TDA4VL)
  • Custom-designed interconnect fabric supporting near max processing entitlement

Memory subsystem:

  • Up to 4MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Two External Memory Interface (EMIF) modules with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266MT/s
    • Two (TDA4VE) or One (TDA4AL/TDA4VL) 32-bit data bus with inline ECC up to 17GB/s per EMIF
  • General-Purpose Memory Controller (GPMC)
  • One (TDA4AL/TDA4VL) or Two (TDA4VE) 512KB on-chip SRAM in MAIN domain, protected by ECC

Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
  • Developed for functional safety applications
  • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
  • Systematic capability up to ASIL-D/SIL-3 targeted
  • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
  • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
  • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
  • Safety-related certification
    • ISO 26262 planned

Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

High speed serial interfaces:

  • One PCI-Express (PCIe) Gen3 controllers
    • Up to four lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Two CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane

Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

Display subsystem:

  • One (TDA4AL/TDA4VL) or Two (TDA4VE) DSI 4L TX (up to 2.5K)
  • One eDP 4L (TDA4VE/TDA4VL)
  • One DPI

Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

Video acceleration:

  • TDA4VE: H.264/H.265 Encode/Decode (up to 480MP/s)
  • TDA4AL: H.264/H.265 Encode only (up to 480MP/s)
  • TDA4VL: H.264/H.265 Encode/Decode (up to 240MP/s)

Ethernet:

  • Two RMII/RGMII interfaces

Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI, and
    • One QSPI

System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 23mm x 23mm, 0.8-mm pitch, 770-pin FCBGA (ALZ)

Companion Power Management ICs (PMIC):

  • Functional Safety-Compliant support up to ASIL-D / SIL-3 targeted
  • Flexible mapping to support different use cases

Processor cores:

  • Two C7x floating point, vector DSP, up to 1.0GHz, 160GFLOPS, 512GOPS
  • Deep-learning matrix multiply accelerator (MMA), up to 8TOPS (8b) at 1.0GHz
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2GHz
    • 1MB shared L2 cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Up to Six Arm Cortex-R5F MCUs at up to 1.0GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Four (TDA4VE) or Two (TDA4AL/TDA4VL) Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800MHz, 50GFLOPS, 4GTexels/s (TDA4VE and TDA4VL)
  • Custom-designed interconnect fabric supporting near max processing entitlement

Memory subsystem:

  • Up to 4MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Two External Memory Interface (EMIF) modules with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266MT/s
    • Two (TDA4VE) or One (TDA4AL/TDA4VL) 32-bit data bus with inline ECC up to 17GB/s per EMIF
  • General-Purpose Memory Controller (GPMC)
  • One (TDA4AL/TDA4VL) or Two (TDA4VE) 512KB on-chip SRAM in MAIN domain, protected by ECC

Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
  • Developed for functional safety applications
  • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
  • Systematic capability up to ASIL-D/SIL-3 targeted
  • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
  • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
  • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
  • Safety-related certification
    • ISO 26262 planned

Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

High speed serial interfaces:

  • One PCI-Express (PCIe) Gen3 controllers
    • Up to four lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Two CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane

Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

Display subsystem:

  • One (TDA4AL/TDA4VL) or Two (TDA4VE) DSI 4L TX (up to 2.5K)
  • One eDP 4L (TDA4VE/TDA4VL)
  • One DPI

Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

Video acceleration:

  • TDA4VE: H.264/H.265 Encode/Decode (up to 480MP/s)
  • TDA4AL: H.264/H.265 Encode only (up to 480MP/s)
  • TDA4VL: H.264/H.265 Encode/Decode (up to 240MP/s)

Ethernet:

  • Two RMII/RGMII interfaces

Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI, and
    • One QSPI

System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 23mm x 23mm, 0.8-mm pitch, 770-pin FCBGA (ALZ)

Companion Power Management ICs (PMIC):

  • Functional Safety-Compliant support up to ASIL-D / SIL-3 targeted
  • Flexible mapping to support different use cases

The TDA4VE TDA4AL TDA4VL processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The TDA4AL provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview: The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to four Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs. To further the integration, the TDA4VE TDA4AL TDA4VL family also includes an MCU island eliminating the need for an external system microcontroller.

The TDA4VE TDA4AL TDA4VL processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The TDA4AL provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview: The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to four Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs. To further the integration, the TDA4VE TDA4AL TDA4VL family also includes an MCU island eliminating the need for an external system microcontroller.
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類型 標題 日期
* Data sheet TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0 datasheet (Rev. B) PDF | HTML 2024年 12月 13日
* Errata J721S2, TDA4VE, TDA4AL, TDA4VL, AM68A Processor Silicon Errata (Rev. C) PDF | HTML 2024年 7月 24日
* User guide J721S2, TDA4AL, TDA4VL, TDA4VE, AM68A Technical Reference Manual (Rev. E) PDF | HTML 2024年 10月 2日
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 2024年 8月 5日
Application note Debugging GPU Driver Issues on TDA4x and AM6x Devices PDF | HTML 2024年 6月 20日
Application note Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 2024年 6月 4日
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 2024年 4月 4日
Technical article Four power supply challenges in ADAS front camera designs PDF | HTML 2024年 1月 5日
Functional safety information J721E, J721S2, J7200, J784S4 MCAL TUV Certification 2023年 12月 22日
Application note Jacinto7 HS Device Customer Return Process PDF | HTML 2023年 11月 16日
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. C) 2023年 9月 11日
User guide AM68 Power Estimation Tool User’s Guide (Rev. A) PDF | HTML 2023年 5月 16日
White paper 以高度整合處理器設計高效邊緣 AI 系統 (Rev. A) PDF | HTML 2023年 4月 19日
User guide Powering Jacinto 7 SoC For Isolated Power Groups With TPS6594133A-Q1 + Dual HCPS PDF | HTML 2023年 3月 1日
Application note UART Log Debug System on Jacinto 7 SoC PDF | HTML 2023年 1月 9日
User guide SK-AM68 Process Starter Kit User's Guide PDF | HTML 2023年 1月 5日
User guide J721S2/TDA4VE/TDA4VL/TDA4AL EVM User Guide PDF | HTML 2022年 12月 2日
Functional safety information Jacinto™ 7 Safety Product Overview PDF | HTML 2022年 8月 15日
Application note Dual-TDA4x System Solution PDF | HTML 2022年 4月 29日
Application note SPI Enablement & Validation on TDA4 Family PDF | HTML 2022年 4月 5日
Technical article How are sensors and processors creating more intelligent and autonomous robots? PDF | HTML 2022年 3月 29日
Technical article How to simplify your embedded edge AI application development PDF | HTML 2022年 1月 28日
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 2022年 1月 10日
Application note TDA4 Flashing Techniques PDF | HTML 2021年 7月 8日
White paper Security Enablers on Jacinto™ 7 Processors 2021年 1月 4日
White paper Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors 2020年 10月 22日
Application note OSPI Tuning Procedure PDF | HTML 2020年 7月 8日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

J721EXCPXEVM — 適用於 Jacinto™ 7 處理器的通用處理器電路板

適用於 Jacinto™ 7 處理器的 J721EXCP01EVM 通用處理器電路板，可讓您評估汽車與工業市場的視覺分析與網路應用。通用處理器電路板相容於所有 Jacinto 7 處理器系統模組 (單獨出售或搭售)，並且包含與輸入/輸出、 JTAG 和各種擴充卡間的基本連線功能。

此多部分評估平台旨在降低整體評估成本、加快開發速度並縮短上市時間。

此 EVM 受處理器 SDK-Vision 支援，其中包含基礎驅動器、運算與視覺核心，以及範例應用架構與示範，可說明如何運用 Jacinto 7 處理器的強大異質架構。

使用指南: PDF | HTML
TI.com 無法提供
開發板

J721S2XSOMXEVM — TDA4VE、TDA4VL 與 TDA4AL 系統模組

J721S2XSOMXEVM 系統模組 (SoM) — 與 J721EXCPXEVM 通用處理器板配對時 — 是評估 Jacinto™ 7 TDA4VE-Q1、TDA4VL-Q1 及 TDA4AL-Q1 的開發平台，適用於在汽車與工業市場中進行視覺分析與網路應用。這些處理器在先進駕駛輔助系統 (ADAS) 網域控制、環景攝影機和自動停車應用中的性能表現尤佳。

TDA4VE-Q1、TDA4VL-Q1 及 TDA4AL-Q1 採用功能強大的異質架構，其中包括固定與浮點數位訊號處理器 (DSP) 核心、Arm® Cortex®-A72 核心、適用於機器學習的矩陣數學加速、整合式 (...)

使用指南: PDF | HTML
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開發板

J7EXPCXEVM — 閘道/乙太網路交換器擴充卡

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our Gateway/Ethernet switch expansion card.

使用指南: PDF | HTML
TI.com 無法提供
開發板

J7EXPEXEVM — 音訊和顯示擴充卡

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our audio and display expansion card.
使用指南: PDF | HTML
TI.com 無法提供
開發板

PHYTC-3P-PHYCORE-AM68 — 適用於 AM68x 和 TDA4VE/AL/VL 處理器的 PHYTEC phyCORE-AM68 系統模組

phyCORE®-AM68A 的特點是系統整合、可延展性和可節省成本。此處理器結合深度學習加速器、向量處理、通用微處理器以及整合式成像子系統，讓 phyCORE-AM68x/TDA4x 成為各種工業應用的絕佳解決方案，例如機器人、機器視覺、雷達等。在系統模組 (SOM) 上整合記憶體、乙太網路 PHY、DSI 至 LVDS 轉換器後，可降低產品開發的複雜性並縮減範圍和成本，而針腳配置則可確保控制器的所有功能皆可使用。

phyCORE-AM68x/TDA4x SOM 可裝入下列任何處理器裝置：AM68、AM68A、TDA4VE、TDA4VL、TDA4AL。

從：PHYTEC
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偵錯探測器

TMDSEMU110-U — XDS110 JTAG 偵錯探測器

德州儀器 XDS110 是一種全新的偵錯探測器 (模擬器) 類別，適用於 TI 嵌入式處理器。XDS110 取代 XDS100 系列，可在單一 Pod 中支援更廣泛的標準 (IEEE1149.1、IEEE1149.7、SWD)。此外，所有 XDS 偵錯探測器均支援具嵌入式追踪緩衝區 (ETB) 的 Arm® 與 DSP 處理器中的核心和系統追蹤功能。透過針腳進行核心追蹤則需要 XDS560v2 PRO TRACE。

德州儀器 XDS110 透過 TI 20 針腳連接器 (配備適用 TI 14 針腳、Arm 10 針腳和 Arm 20 針腳的多重轉接器) (...)

使用指南: PDF
TI.com 無法提供
偵錯探測器

TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現，支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (480Mbps) (...)

TI.com 無法提供
軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-J721S2 — Linux® SDK for TDA4VE, TDA4VL and TDA4AL

The J721S2 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4VL-Q1 and TDA4AL-Q1 system-on-a-chip (SoCs) within our Jacinto™ platform.

(...)

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產品
Arm 式處理器
TDA4AL-Q1 — 使用攝影機和雷達感測器，且適用前攝影機與 ADAS 網域控制的車用系統單晶片 TDA4VE-Q1 — 具 AI、視覺預處理和 GPU，且適用自動停車和駕駛輔助的車用系統單晶片 TDA4VL-Q1 — 具 AI、視覺處理且適用環景系統與停車輔助應用的車用系統單晶片
硬體開發
開發板
J721S2XSOMXEVM — TDA4VE、TDA4VL 與 TDA4AL 系統模組
下載選項
軟體開發套件 (SDK)

PROCESSOR-SDK-QNX-J721S2 — QNX SDK for TDA4VE, TDA4VL and TDA4AL

The J721S2 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4VL-Q1 and TDA4AL-Q1 system-on-a-chip (SoCs) within our Jacinto™ platform.

(...)

支援產品和硬體

支援產品和硬體

產品
Arm 式處理器
TDA4AL-Q1 — 使用攝影機和雷達感測器，且適用前攝影機與 ADAS 網域控制的車用系統單晶片 TDA4VE-Q1 — 具 AI、視覺預處理和 GPU，且適用自動停車和駕駛輔助的車用系統單晶片 TDA4VL-Q1 — 具 AI、視覺處理且適用環景系統與停車輔助應用的車用系統單晶片
硬體開發
開發板
J721S2XSOMXEVM — TDA4VE、TDA4VL 與 TDA4AL 系統模組
下載選項
軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-J721S2 — RTOS SDK for TDA4VE, TDA4VL and TDA4AL

The J721S2 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4VL-Q1 and TDA4AL-Q1 system-on-a-chip (SoCs) within our Jacinto™ platform.

(...)

支援產品和硬體

支援產品和硬體

產品
Arm 式處理器
TDA4AL-Q1 — 使用攝影機和雷達感測器，且適用前攝影機與 ADAS 網域控制的車用系統單晶片 TDA4VE-Q1 — 具 AI、視覺預處理和 GPU，且適用自動停車和駕駛輔助的車用系統單晶片 TDA4VL-Q1 — 具 AI、視覺處理且適用環景系統與停車輔助應用的車用系統單晶片
硬體開發
開發板
J721S2XSOMXEVM — TDA4VE、TDA4VL 與 TDA4AL 系統模組
下載選項
IDE、配置、編譯器或偵錯程式

C7000-CGT — C7000 代碼產生工具 - 編譯器

The TI C7000 C/C++ Compiler Tools support development of applications for TI C7000 Digital Signal Processor cores.

Code Composer Studio is the Integrated Development Environment (IDE) for TI embedded devices.  If you are looking to develop on a TI embedded device it is recommended to start (...)
使用指南: PDF | HTML
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

支援產品和硬體

支援產品和硬體

此設計資源支援此類別中多數產品。

檢查產品詳細資料頁面以確認支援。
啟動 下載選項
IDE、配置、編譯器或偵錯程式

SAFETI_CQKIT — 安全編譯器資格套件

The Safety Compiler Qualification Kit was developed to assist customers in qualifying their use of the TI ARM, C6000, C7000 or C2000/CLA C/C++ Compiler to functional safety standards such as IEC 61508 and ISO 26262.

The Safety Compiler Qualification Kit:

  • is free of charge for TI customers
  • does (...)
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IDE、配置、編譯器或偵錯程式

SYSCONFIG — 系統配置工具

SysConfig 是一款配置工具，專門設計用來簡化硬體與軟體配置挑戰，進而加速軟體開發。

SysConfig 是 Code Composer Studio™ 整合式開發環境的一部分，也是一個獨立式應用。此外，您也可造訪 TI開發人員區在雲端執行 SysConfig。

SysConfig 提供直覺式圖形使用者介面，可用於配置針腳、周邊設備、無線電、軟體堆疊、RTOS、時脈樹和其他元件。SysConfig 會自動偵測、找出並解決衝突，以加速軟體開發。

View Options
支援軟體

EXLFR-3P-ESYNC-OTA — 適用於軟體定義車輛的 Excelfore esync OTA 無線更新

Experience the future of the connected SDV starting with full vehicle OTA from Excelfore. The standardized and structured eSync pipeline securely scales to reach all the ECUs and smart sensors in the car, with the flexibility to cover any in-vehicle network topology or system architecture.
eSync (...)
從：ExcelFore
造訪合作夥伴網站
支援軟體

EXLFR-3P-TSN — 適用於重要安全通訊的 ExelFore 的時效性網路 (TSN) 汽車路徑

軟體定義車輛 (SDV) 需要高性能網路、IP 定址和安全性，這些可透過乙太網路提供，但無法透過 CAN 提供。汽車應用也需要確保重要安全系統的延遲、頻寬和備援，這些是基本乙太網路無法提供的，但是 TSN 增加了這些功能。Excelfore 的 AVB/TSN 已通過 AVNU 認證。
乙太網路技術能以具成本效益的方式，將車內頻寬從 10MB 分支擴充至 10GB 以上。它還提供動態網路切換、網路安全性，而且能夠從雲端連線裝置。Excelfore 的 SOME/IP、DoIP、RTP、RTCP 和 UDS 通訊協定可將傳統系統帶入 SDV 時代，無縫整合至乙太網路骨幹，為 CAN (...)
從：ExcelFore
造訪合作夥伴網站
支援軟體

PAI-3P-PHANTOMVISION — 適用 ADAS 汽車應用且在 Jacinto 處理器上執行的 Phantom AI 視覺軟體

PhantomVision™ is a scalable, flexible and reliable deep learning based computer vision solution that provides a comprehensive suite of Euro NCAP compliant ADAS features. It is a visual perception engine that enables a single or multiple cameras to autonomously recognize road objects and (...)
從：Phantom AI
造訪合作夥伴網站
模擬型號

AM68 TDA4VE TDA4AL TDA4VL BSDL MODEL

SPRM837.ZIP (13 KB) - BSDL Model
下載
模擬型號

AM68A,TDA4VE,TDA4AL,TDA4VL IBIS MODEL

SPRM839.ZIP (1476 KB) - IBIS Model
下載
封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (ALZ) 770 Ultra Librarian
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