產品詳細資料

Function General-purpose timer Iq (typ) (mA) 0.18 Rating Catalog Operating temperature range (°C) -40 to 125 Supply voltage (max) (V) 15 Supply voltage (min) (V) 2
Function General-purpose timer Iq (typ) (mA) 0.18 Rating Catalog Operating temperature range (°C) -40 to 125 Supply voltage (max) (V) 15 Supply voltage (min) (V) 2
PDIP (P) 8 92.5083 mm² 9.81 x 9.43 SOIC (D) 8 29.4 mm² 4.9 x 6 SOP (PS) 8 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Very low power consumption:
    • 1-mW typical at V DD = 5 V
  • Capable of operation in astable mode
  • CMOS output capable of swinging rail to rail
  • High output current capability
    • Sink: 100-mA typical
    • Source: 10-mA typical
  • Output fully compatible with CMOS, TTL, and MOS
  • Low supply current reduces spikes during output transitions
  • Single-supply operation from 2 V to 15 V
  • Functionally interchangeable with the NE555; has same pinout
  • ESD protection exceeds 1000 V per ANSI/ESDA/JEDEC JS-001
  • Available in Q-temp automotive
    • High-reliability automotive applications
    • Configuration control and print support
    • Qualification to automotive standards
  • Very low power consumption:
    • 1-mW typical at V DD = 5 V
  • Capable of operation in astable mode
  • CMOS output capable of swinging rail to rail
  • High output current capability
    • Sink: 100-mA typical
    • Source: 10-mA typical
  • Output fully compatible with CMOS, TTL, and MOS
  • Low supply current reduces spikes during output transitions
  • Single-supply operation from 2 V to 15 V
  • Functionally interchangeable with the NE555; has same pinout
  • ESD protection exceeds 1000 V per ANSI/ESDA/JEDEC JS-001
  • Available in Q-temp automotive
    • High-reliability automotive applications
    • Configuration control and print support
    • Qualification to automotive standards

The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS™ technology. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of a high input impedance, this device supports smaller timing capacitors than those supported by the NE555 or LM555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs must be tied to an appropriate logic level to prevent false triggering.

The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS™ technology. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of a high input impedance, this device supports smaller timing capacitors than those supported by the NE555 or LM555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs must be tied to an appropriate logic level to prevent false triggering.

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類型 標題 日期
* Data sheet TLC555 LinCMOS™ Technology Timer datasheet (Rev. J) PDF | HTML 2023年 11月 27日
Circuit design Frequency-to-Voltage Conversion Circuit Using a 555 Timer 2023年 9月 21日
Application note Considering TI Smart DACs As an Alternative to 555 Timers PDF | HTML 2021年 9月 2日
More literature Design low-duty-cycle timer circuits 2016年 10月 3日
Application note TLC555-Q1 Used as a Positive and Negative Charge Pump 2016年 5月 25日
Application note Synchronizing Three or More UCC28950 Phase-Shifted, Full-Bridge Controllers 2011年 9月 13日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

TLC555 TINA-TI Astable Reference Design (Rev. B)

SLFM002B.TSC (100 KB) - TINA-TI Reference Design
模擬型號

TLC555 TINA-TI Mono Reference Design (Rev. B)

SLFM003B.TSC (102 KB) - TINA-TI Reference Design
模擬型號

TLC555 TINA-TI Spice Model

SLFM005.ZIP (9 KB) - TINA-TI Spice Model
模擬型號

TLC555x and TLC556x PSpice Model (Rev. E)

SLFJ002E.ZIP (25 KB) - PSpice Model
計算工具

TLC555CALC TLC555 Design Calculator

This spreadsheet calculates the complete design of a TLC555 timer-based astable circuit given the timing capacitance, on time, and desired duty cycle. Resistor values are calculated to the nearest 1% value.
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
參考設計

PMP20967 — 適用於瞬態測試的可調整的雙級定電流負載參考設計

這套可調式雙級定電流負載參考設計,可協助工程師利用特殊功能及簡易操作來測試電源供應器輸出負載瞬態回應。其電路板爲低電平和高電平提供負載瞬態調整,電壓轉換率可高達 100 A/µs。電路板上還設計了時序調整,如時間週期、延遲和脈衝寬度。
Test report: PDF
參考設計

TIDA-010085 — 使用數位隔離器的 24-VAC 多通道固態繼電器參考設計

此參考設計展示使用單一隔離的多通道固態繼電器 (SSR)。此設計採用含單一隔離式電源供應器與通用接地閘極驅動電路的多通道數位隔離器,以獨立控制多個 SSR。此設計適用 24-VAC 供電繼電器,額定電流可達 2A,但可擴充至 240VAC 和更高的額定電流。每個 SSR 通道消耗的空間小於 75 mm 2,組件的最大高度約爲 3 mm,與機電繼電器相比,可大幅節省尺寸。使用單一隔離式電源可減少機板空間及 BOM 成本。
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
PDIP (P) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian
SOP (PS) 8 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian

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  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

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