TLC555
- Very low power consumption:
- 1-mW typical at V DD = 5 V
- Capable of operation in astable mode
- CMOS output capable of swinging rail to rail
- High output current capability
- Sink: 100-mA typical
- Source: 10-mA typical
- Output fully compatible with CMOS, TTL, and MOS
- Low supply current reduces spikes during output transitions
- Single-supply operation from 2 V to 15 V
- Functionally interchangeable with the NE555; has same pinout
- ESD protection exceeds 1000 V per ANSI/ESDA/JEDEC JS-001
- Available in Q-temp automotive
- High-reliability automotive applications
- Configuration control and print support
- Qualification to automotive standards
The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS™ technology. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of a high input impedance, this device supports smaller timing capacitors than those supported by the NE555 or LM555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage.
Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs must be tied to an appropriate logic level to prevent false triggering.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | TLC555 LinCMOS™ Technology Timer datasheet (Rev. J) | PDF | HTML | 2023年 11月 27日 |
Circuit design | Frequency-to-Voltage Conversion Circuit Using a 555 Timer | 2023年 9月 21日 | ||
Application note | Considering TI Smart DACs As an Alternative to 555 Timers | PDF | HTML | 2021年 9月 2日 | |
More literature | Design low-duty-cycle timer circuits | 2016年 10月 3日 | ||
Application note | TLC555-Q1 Used as a Positive and Negative Charge Pump | 2016年 5月 25日 | ||
Application note | Synchronizing Three or More UCC28950 Phase-Shifted, Full-Bridge Controllers | 2011年 9月 13日 |
設計與開發
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TLC555 TINA-TI Astable Reference Design (Rev. B)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TIDA-010085 — 使用數位隔離器的 24-VAC 多通道固態繼電器參考設計
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
PDIP (P) | 8 | Ultra Librarian |
SOIC (D) | 8 | Ultra Librarian |
SOP (PS) | 8 | Ultra Librarian |
TSSOP (PW) | 14 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。