TMUX7219-Q1
- AEC-Q100 qualified for automotive applications
- Device temperature grade 1: –40°C to 125°C ambient operating temperature
- Functional safety-capable
- Latch-up immune
- Dual supply range: ±4.5V to ±22V
- Single supply range: 4.5V to 44V
- Low on-resistance: 2.1Ω
- Low charge injection: −10pC
- High current support: 330mA (maximum)
- 1.8V logic compatible
- Fail-safe logic
- Rail-to-rail operation
- Bidirectional signal path
- Break-before-make switching
The TMUX7219-Q1 is a complementary metal-oxide semiconductor (CMOS) switch with latch-up immunity in a single channel, 2:1 (SPDT) configuration. The device works with a single supply (4.5V to 44V), dual supplies (±4.5V to ±22V), or asymmetric supplies (such as VDD = 12V, VSS = –5V). The TMUX7219-Q1 supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from VSS to VDD.
The TMUX7219-Q1 can be enabled or disabled by controlling the EN pin. When disabled, both signal path switches are off. When enabled, the SEL pin can be used to turn on signal path 1 (S1 to D) or signal path 2 (S2 to D). All logic control inputs support logic levels from 1.8V to VDD, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage.
The TMUX72xx family provides latch-up immunity, preventing undesirable high current events between parasitic structures within the device typically caused by overvoltage events. A latch-up condition typically continues until the power supply rails are turned off and can lead to device failure. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | TMUX7219-Q1 44V , Latch-Up Immune, 2:1 (SPDT) Precision Switch with 1.8V Logic datasheet (Rev. C) | PDF | HTML | 2024年 12月 20日 |
Application note | How to Handle High Voltage Common Mode Applications using Multiplexers | PDF | HTML | 2022年 10月 3日 | |
Application note | Using Latch Up Immune Multiplexers to Help Improve System Reliability (Rev. A) | 2021年 9月 20日 | ||
Functional safety information | TMUX7219-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA | PDF | HTML | 2021年 6月 14日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器
The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages. The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
VSSOP (DGK) | 8 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。